Simplify conditional.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198350 91177308-0d34-0410-b5e6-96231b3b80d8
Fix up a couple of review comments:

Use an if statement instead of a pair of ternary operators checking
the same condition.
Use a cheap method call rather than returning the local symbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198351 91177308-0d34-0410-b5e6-96231b3b80d8
Fix all the verifier tests I added for address spaces.

I originally had these using opt -verify, and I never removed the
-verify when converting them to use llvm-as instead, so these were
failing because of using the -verify argument which llvm-as doesn't have
instead of what it's actually supposed to be testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198352 91177308-0d34-0410-b5e6-96231b3b80d8
indvars: cleanup the IV visitor. It does more than gather sext/zext info.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198353 91177308-0d34-0410-b5e6-96231b3b80d8
Disable compare sinking in CodeGenPrepare when multiple condition registers are available

As noted in the comment above CodeGenPrepare::OptimizeInst, which aggressively
sinks compares to reduce pressure on the condition register(s), for targets
such as PowerPC with multiple condition registers, this may not be the right
thing to do. This adds an HasMultipleConditionRegisters boolean to TLI, and
CodeGenPrepare::OptimizeInst is skipped when HasMultipleConditionRegisters is
true.

This functionality will be used by the PowerPC backend in an upcoming commit.
Especially when the PowerPC backend starts tracking individual condition
register bits as separate allocatable entities (which will happen in this
upcoming commit), this sinking from CodeGenPrepare::OptimizeInst is
significantly suboptimial.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198354 91177308-0d34-0410-b5e6-96231b3b80d8
[PPC] Use the correct immediate operands on 64-bit instructions

Several of the 64-bit fixed-point instructions with immediate operands were
using the 32-bit (i32) operand nodes instead of the corresponding 64-bit (i64)
operand definitions (u16imm instead of u16imm64, for example).

This error has had no effect so far, but would have caused type-checking
violations with an upcoming change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198356 91177308-0d34-0410-b5e6-96231b3b80d8
Revert seemingly unnecessary section sym for the data section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198357 91177308-0d34-0410-b5e6-96231b3b80d8
Elaborate on comment for skeleton CU construction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198358 91177308-0d34-0410-b5e6-96231b3b80d8
[PPC] Fix the scheduling of CR logicals on the P7

CR logicals (crand, crxor, etc.) on the P7 need to be in the first slot of each
dispatch group. The old itinerary entry was just wrong (but has not mattered
because we don't generate these instructions).

This will matter when, in an upcoming commit, we start generating these
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198359 91177308-0d34-0410-b5e6-96231b3b80d8