PR c++/58678
	* g++.dg/abi/thunk6.C: Scan assembler for _ZTv0_n32_N1CD1Ev
	only for lp64 targets and scan for _ZTv0_n16_N1CD1Ev for ilp32
	targets.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208907 138bc75d-0d04-0410-961f-82ee72b054a4
[ARM/AArch64][1/2] Crypto intrinsics tuning for Cortex-A53 - "type" Attribute restructuring

     * config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi):
     Use crypto_aese type.
     (aarch64_crypto_aes<aesmc_op>v16qi): Use crypto_aesmc type.
     * config/arm/arm.md (is_neon_type): Replace crypto_aes with
     crypto_aese, crypto_aesmc.  Move to types.md.
     * config/arm/types.md (crypto_aes): Split into crypto_aese,
     crypto_aesmc.
     * config/arm/iterators.md (crypto_type): Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208908 138bc75d-0d04-0410-961f-82ee72b054a4
[ARM/AArch64][2/2] Crypto intrinsics tuning for Cortex-A53 - pipeline description

	* config/arm/aarch-common.c (aarch_crypto_can_dual_issue): New.
	* config/arm/aarch-common-protos.h (aarch_crypto_can_dual_issue):
	Declare extern.
	* config/arm/cortex-a53.md: Add reservations and bypass for crypto
	instructions as well as AdvancedSIMD loads.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208910 138bc75d-0d04-0410-961f-82ee72b054a4