arm: tegra: enterprise: disable dsi_csi_rail in LP0

AVDD_DSI_CSI is shared by modem and dsi. If DSI turns
off this rail then HSIC fails after wakeup from modem.
This patch provides a way to turn on this rail from
modem as well as from DSI. Create two virtual power rails
from avdd_csi_dsi to control it from both the drivers separately.
This is enterprise specific change as per the power rail layout.

Bug 920881

(cherry picked from commit ab52b51c59f776ae770d48a28a2744e2db2e5d2f)
Reviewed-on: http://git-master/r/85656

Change-Id: I2e9c04a8f4e8d6fd20584b4e75657c1cb6d5c8bd
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/89134
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Conflicts:
	arch/arm/mach-tegra/baseband-xmm-power.c
usb: gadget: fsl_udc: support udc driver without otg

Currently udc driver is dependent on otg driver.
Added irq work to make gadget driver work with
disabling otg driver.

Bug 962366

Change-Id: Id782d8003da12ace553b8b812fa410567c281b34
Reviewed-on: http://git-master/r/95106
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Conflicts:
	drivers/usb/gadget/fsl_udc_core.c
mfd: max8907c: Disable Hard Reset with Power key

Disable Hard Reset on long press of power key.

Bug 893517

Change-Id: Ic328a04e917aa1bed6780e6f9a2f1c575f84fb68
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/96687
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
power: smb349: addition of regulator interface

Addition of reglator interface to detect the usb cable
plug/unplug detection.

Bug 961166
Bug 966874

Change-Id: Ida297bc39df9aca8cffe60c29bc24f2d32819f56
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Signed-off-by: Chandler Zhang <chazhang@nvidia.com>
Reviewed-on: http://git-master/r/96440
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

Conflicts:
	drivers/power/smb349-charger.c
arm: tegra: kai: addition of charger regulator

Use SMB349 regulator instead of irq to controll USB1 VBUS

Bug 961166
Bug 966874

Change-Id: I68884444883277ef169f3eb066ea50d6d49b708d
Signed-off-by: Chandler Zhang <chazhang@nvidia.com>
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/96441
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
arm: tegra: grouper: addition of charger regulator

Use SMB349 regulator instead of irq to controll USB1 VBUS
ARM: tegra: usb: kai: pmu int not required

vbus int can be generated from pmu and directly from port
when host mode is reqruied, we use vbus int and pmu int
is not required as usb clock is not disabled.

Bug 961166

Change-Id: I96fde7daf052a7c5b8e94414e309b0be6354ec80
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/96338
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chandler Zhang <chazhang@nvidia.com>
Tested-by: Chandler Zhang <chazhang@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
ARM: tegra: usb: grouper: pmu int not required

vbus int can be generated from pmu and directly from port
when host mode is reqruied, we use vbus int and pmu int
is not required as usb clock is not disabled.
i2c: tegra: support for I2C_M_NOSTART protocol mangling

Adding support for protocol mangling I2C_M_NOSTART.

Change-Id: I6cc0c96b3c374d452ea886a0f983dc5d31c4575c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/92573
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: cardhu: pm299: enable 3v3 rail during boot

Enabling the 3v3 voltage rail during boot.
bug 822562

Change-Id: I15318b0c30bae716f40985cbee06cd9eaff54ee3
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/96685
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
arm: tegra: resolve compilation time warnings

Bug 949219

Change-Id: I875f8688a272c415ebf345b8f30e4afdf7551b29
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/91523
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Conflicts:
	arch/arm/mach-tegra/baseband-xmm-power.c
arm: tegra: grouper: resolve compilation time warnings

Apply for grouper too
ASoC: resolve compilation time warnings

bug 949219

Change-Id: I52969e8dd1a5ed4dc76ac360ec08b0afb18cd4a5
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/92833
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Conflicts:
	sound/soc/tegra/tegra_rt5640.c
ARM: tegra: remove T30 FPGA support

Remove T30 FPGA support as it will conflict with downstreaming mainline
way of using chipid and revision.

Change-Id: Ic1fd1107801de13c265c7dde8571e0537c43f4fd
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/95872
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
drivers: resolve compilation time warnings

bug 949219

Change-Id: I5942ba86bd1cbe1f1bd06a7c9f51a10d83e6cabb
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/92819
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Revert "ARM: tegra30: pm: flush L1 data before exit coherency on secondary CPU"

This reverts commit 743c03fbeb5908faf4aef6bee7702a2ad4caac22.

Bug 967887

Change-Id: Ie4477e3b5fa9773c9e60b5cace47b3ff240a4bf1
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/96785
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Revert "ARM: tegra20: pm: flush L1 data before exit coherency"

This reverts commit 209209a303742d6312f66896b4351dd97e48e24c.

Bug 967887

Change-Id: I2464db28b5a4970d6e60ef79c89c2107c64cb6d3
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/96786
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Revert "ARM: tegra: rethink the cpu suspend-resume code path"

This reverts commit f31ca2d9e0580b58dc51fde31fc8ace190dd253b.

Bug 967887

Change-Id: I3fe975f7a6939cace5e208947bcb82e09008c0ac
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/96787
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Revert "ARM: tegra: remove usage of USE_TEGRA_CPU_SUSPEND"

This reverts commit e6d0e0ceec7cd1a7b8085eb31d2e70bc4d15684f.

Bug 967887

Change-Id: I60927a93ebdf6ba4da14311f8ffcc1edf4f56391
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/96788
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Restore "ARM: tegra: power: Workaround PMD corruption by cpu_resume_mmu"

This restores commit 607d5ec8bb46f95473533f611da1ffc97907d16e.

The common ARM CPU state suspend/resume code does not work with
and external L2 cache controller (like a PL310) enabled. This
change fixes corruption of the current PMD by the MMU resume code.

cpu_resume_mmu modifies the currently active page tables to add
a flat (VA==PA) section mapping of cpu_resume_turn_mmu_on to
handle MMU off-to-on transition. It turns off the L1 data cache
but it knows nothing of the L2 cache. Since page table walks are
L2 cacheable, other CPUs in the system can pick up the corrupted
PMD which will eventually result in a kernel panic.

The workaround for this is to modify push_ctx_regs to save the
current TTB0 and CONTEXID registers in the CPU register context
and switch to the private tegra_pgd before saving the rest of the
CPU context. The tegra_pgd already has a flat mapping for the
code in question, so it can't be damaged by the actions of
cpu_resume_mmu. Likewise, pop_ctx_regs is modified to restore
the actual TTB0 and CONTEXTID registers when restoring the CPU
registers.

Bug 967887

Change-Id: Iaf98c46359860531874354e8cddabe299ea90d57
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/96789
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>