new data/shift_in is now read on rising_edge and shifting now happens on falling edge
removed shift_in latch because this is now handled in the shift register
removed shift_in latch because this is now handled in the shift register
shift register now follows the slave clock
rearranged if statements
increased length reg_set signal
shift_reg now works on inverted clock so it is in sync with the slave clock
finished modelsim simulation of spi_rework branch
now shifts on the falling_edge
latched miso on rising_edge of the sclk
spi_slave no longer requires a clk signal it is now al based on the slave clock
it is no longer a state machine, the outputs are now based on the counter which counts the sclk
minor changes that need to be simulated in modelsim again
redid modelsim simulation
spi_slave component was changed
data buffer removed data_ready bit now indicates when data is ready
full master slave synthesized in GWTF
fixed last few timing errors
Merge branch 'spi_rework'

Conflicts:
	chip/subsystems/SPI/spi.vhd
	chip/subsystems/SPI/spi_slave.vhd