issue: reduce fan-out on mispredict
dpram: "old data" style for faster synthesis
pipeline: move backpressure from fifo to renamer

To make good use of reservation stations, we need to refill them
quickly once they are committed. Trying to use tokens in the FIFO
for this adds too many cycles of latency, wasting FIFO slots.

This commit puts the back-pressure in the renamer, which means
that a reservation station is only wasted for 2 cycles:
  useful data in station     (r_stat_reg*)
  commit decision            (r_done_regx => commit_stb)
  station readiness check    (r_ren_stb => s_ren_done_a)
renamer: is lower-left triangular, not LR
commit: prototype core for retiring instructions
fifo: adding glue to connect the pieces together
opa: enough pieces to run simulation!
opa: simulation compiles it
opa: connect execution units
opa: tidy up reset/mispredict logic

most importantly, fill in the FIFO on reset
fifo: mispredict must also clear the dpram's address
opa: missing connections
renamer: update architecture map only with a strobe
renamer: a != b
opa: bigendian instruction format
issue: load stations correctly
decoder: pick a type (1-hot!)
opa: wire the execution units to the issuer
fifo: carry setx properly
renamer: back pressure must come from station being pushed to issue