de1: remove wb_data_resize from orpsoc_top.v

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
adv_debug_sys: fix 32 bits wb access in jsp module

Old code depends on address bits [1:0] to be update during
a 8 bits access on a 32 bits bus. The OR1200 does that.

Because it is not in the wishbone specification, we can't rely
on this. For example, mor1kx set address bits [1:0] to "00".

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
mt48lc16m16a2: Add convenience wrapper for test benches

This adds a wrapper that takes care of preloading RAM from ELF files
and adds simulated delay on the data lines.
mt48lc16m16a2: Add wrapper file to .core