switch to faster synthesis settings while I work on getting
CPU timing reasonable.
push shadow ram address out faster to improve timing.
reindent file
split instruction dispatch into two cycles to improve timing.
re-enable pushing of PC at start of JSR now that it happens in
Cycle3 which has improved timing.
flatten memory access logic to improve timing.
add missing signals to sensitivity lists.
fix memory read address generation bug in branches.
temporarily reduce CPU to 32MHz while optimising critical path
to make synthesis run faster.
put cpu back to 64MHz since critial paths don't show anyway (due
to matching with io clock).
begin adding in stereo SIDs
add SID VHDL modules to ISE project
put SIDs into IO memory map.
tri-state SID data lines.
plumb SID audio through to 3.5mm jack.