[AArch64] Logical vector shift right conformance

gcc/

	* config/aarch64/aarch64-simd-builtins.def (lshr): DI mode excluded.
	(lshr_simd): DI mode added.
	* config/aarch64/aarch64-simd.md (aarch64_lshr_simddi): New pattern.
	(aarch64_ushr_simddi): Likewise.
	* config/aarch64/aarch64.md (UNSPEC_USHR64): New unspec.
	* config/aarch64/arm_neon.h (vshr_n_u64): Intrinsic fixed.
	(vshrd_n_u64): Likewise.

gcc/testsuite/

	* gcc.target/aarch64/ushr64_1.c: New testcase.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@208789 138bc75d-0d04-0410-961f-82ee72b054a4