gallium/i915: handle query_renderer caps

Implementation based on the classic driver with the following
changes:
 - Use auxiliarry function os_get_total_physical_memory to get the
total amount of memory.
 - Move the libdrm_intel specific get_aperture_size to the winsys.

Cc: Stephane Marchesin <stephane.marchesin@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
gallium/ilo: handle query_renderer caps

Implementation based on the classic driver with the following
changes:
 - Use auxiliarry function os_get_total_physical_memory to get the
total amount of memory.
 - Move the libdrm_intel specific get_aperture_size to the winsys.

Cc: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
gallium/r300/r600/radeonsi: handle query_renderer caps

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
gallium/vc4: handle query_renderer caps

Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
gallium/nouveau: handle query_renderer caps

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
gallium/svga: handle query_rendered caps

All the values are are currently hardcoded. One could use
some heuristics to determine the amount of video memory if
a callback to the host is not available.

Do we what to advertise the driver as hardwar accelerated ?

Cc: Brian Paul <brianp@vmware.com>
Cc: José Fonseca <jose.r.fonseca@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
gallium/softpipe/llvmpipe: handle query_renderer caps

Both report 0xffffffff as both vendor and device id, and the maximum
amount of system memory as video memory.

v2: Use aux helper os_get_total_physical_memory().

Cc: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
st/dri: Add __DRI2rendererQueryExtension support

The final step to get GLX_MESA_query_renderer working with gallium
drivers.

v2: Remove __DRI2_RENDERER_PREFERRED_PROFILE handling. It's already
handled in dri/common. Spotted by Marek.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
docs/autoconf: explicitly mention PKG_CONFIG_PATH for cross/multilib builds

... and squash a couple of typos.

Suggested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
i965: Add an option to not generate the SIMD8 fragment shader

For now, this can only be triggered with a new 'no8' INTEL_DEBUG option
and a new context flag.  We'll use the context flag later, but introducing
it now lets us bisect to this commit if it breaks something.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add context flag to disable the viewport transform

This lets us disable the viewport transform, which will be useful for
emitting 3DPRIM_RECTLIST.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add a mechanism for sending native primitives into the driver

The brw_draw_prims() function is the draw entry point into the driver,
and takes struct _mesa_prim for input.  We want to be able to feed
native primitives into the driver, and to that end we introduce
BRW_PRIM_OFFSET, which lets use describe geometry using the native
GEN primitive types.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Disable clipping when rendering 3DPRIM_RECTLIST primitives

The clipper doesn't support clipping 3DPRIM_RECTLIST primitives and must
be turned off when we use them.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Provide a context flag to let us enable fast clear

GEN7+ has the fast clear functionality, which lets us clear the color
buffers using the MCS and a scaled down rectangle.  To enable this
we have to set the appropriate bits in the 3DSTATE_PS package.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Move pre-draw resolve buffers to dd::UpdateState

No functional change except for glBegin/glEnd style rendering, where we now
do the resolves at glBegin time instead of FLUSH_VERTICES time.  This is also
the reason for this change, so that when we later switch fast clear resolve to
use meta, we won't be doing meta operations in the middle of a begin/end
sequence.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
mesa: Use _mesa_lock_context_textures in _mesa_GetTexParameterfv()

GetTexParamterfv() doesnt change texture state, so instead of
_mesa_lock_texture() we can use _mesa_lock_context_textures(),
which doesn't increase the texture stamp.  With this change,
_mesa_update_state_locked() is now only called from under
_mesa_lock_context_textures(), which is right thing to do.  Right now
it's the same mutex, but if we made texture locking more fine grained
locking one day, just locking one texture here would be wrong.

This all ignores the fact that texture locking seem a bit
flaky and broken, but we're trying to not blatantly make it worse.

This change allows us to reliably unlock the context textures in the
dd::UpdateState callback as is necessary for meta color resolves.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
meta: Export _mesa_meta_drawbuffers_from_bitfield()

We'll use this in the i965 fast clear implementation.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
i965: Add optimization pass to let us use the replicate data message

The data port has a SIMD16 'replicate data' message, which lets us write
the same color for all 16 pixels by sending the four floats in the
lower half of a register instead of sending 4 times 16 identical
component values in 8 registers.

The message comes with a lot of restrictions and could be made generally
useful by recognizing when those restriction are satisfied.  For now,
this lets us enable the optimization when we know it's safe, but we don't
enable it by default.  The optimization works for simple color clear shaders
only, but does recognized and support multiple render targets.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Implement fast color clears using meta operations

This patch uses the infrastructure put in place by previous patches
to implement fast color clears and replicated color clears in terms of
meta operations.

This works all the way back to gen7 where fast clear was introduced and
adds support for fast clear on gen8.  It replaces the blorp path
completely and improves on a few cases.  Layered clears are now done
using instanced rendering and multiple render-target clears use a
MRT shader with rep16 writes.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
vc4: Move the deref of the color buffer for simulator into the simulator.

At some point I'm going to want to move the information necessary for the
host buffer upload/download into the BO so that it's independent of the
current vc4->framebuffer, but for now this fixes pointless derefs on
non-simulator in vc4_context.c since the dump_fbo() removal