Daily computer-to-computer commit:
Modified:
        shiftreg.v -- Modified so that first index is no longer combinational input (changes output indexing)
        rx_engine.v -- Indexing changes (from shiftreg)
        rxc_enabler -- Indexing changes (from shiftreg)
        rxr_enabler -- Indexing changes (from shiftreg)
                       Added bar decode enable
        rxr_engine -- Indexing changes (from shiftreg).
                      Added bar decode enable & output
                      Updated enable indexing parameters
                      Removed mux from Addr High bits (replaced with direct wiring/reset)
                      Added EOF/SOF calculations
        rxc_engine -- Indexing changes (from shiftreg)
        trellist.vh -- No changes to defines, but did add clog function
                       Need to fix problems with clog function declaration in verilator