[AVX512] Fix miscompile for unpack

r189189 implemented AVX512 unpack by essentially performing a 256-bit unpack
between the low and the high 256 bits of src1 into the low part of the
destination and another unpack of the low and high 256 bits of src2 into the
high part of the destination.

I don't think that's how unpack works.  AVX512 unpack simply has more 128-bit
lanes but other than it works the same way as AVX.  So in each 128-bit lane,
we're always interleaving certain parts of both operands rather different
parts of one of the operands.

E.g. for this:
__v16sf a = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
__v16sf b = { 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 };
__v16sf c = __builtin_shufflevector(a, b, 0, 8, 1, 9, 4, 12, 5, 13, 16,
	    			       	     24, 17, 25, 20, 28, 21, 29);

we generated punpcklps (notice how the elements of a and b are not interleaved
in the shuffle).  In turn, c was set to this:

  0 16 1 17 4 20 5 21 8 24 9 25 12 28 13 29

Obviously this should have just returned the mask vector of the shuffle
vector.

I mostly reverted this change and made sure the original AVX code worked
for 512-bit vectors as well.

Also updated the tests because they matched the logic from the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217602 91177308-0d34-0410-b5e6-96231b3b80d8
Added missing LLVM_NOEXCEPT to the definition of _obj2yaml_error_category::name

LLVM_NOEXCEPT was added in r210591.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217603 91177308-0d34-0410-b5e6-96231b3b80d8
[MCJIT] Take the relocation addend into account when applying ARM MachO VANILLA
and BR24 relocations.

<rdar://problem/18296496>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217605 91177308-0d34-0410-b5e6-96231b3b80d8
Add DAG combine for shl + add of constants.

Do
 (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)

This is already done for multiplies, but since multiplies
by powers of two are turned into shifts, we also need
to handle it here.

This might want checks for isLegalAddImmediate to avoid
transforming an add of a legal immediate with one that isn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217610 91177308-0d34-0410-b5e6-96231b3b80d8
Provide an implementation of getNoopForMachoTarget for SPARC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217611 91177308-0d34-0410-b5e6-96231b3b80d8
Add triple to test to fix bots

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217612 91177308-0d34-0410-b5e6-96231b3b80d8
Use the simpler sys::fs:;exists. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217617 91177308-0d34-0410-b5e6-96231b3b80d8
Use simpler version of sys::fs::exists. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217618 91177308-0d34-0410-b5e6-96231b3b80d8
[MCJIT] Add support for ARM HALF_DIFF relocations to MCJIT.

Fixes <rdar://problem/18297804>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217620 91177308-0d34-0410-b5e6-96231b3b80d8
[PATCH, PowerPC] Accept 'U' and 'X' constraints in inline asm

Inline asm may specify 'U' and 'X' constraints to print a 'u' for an
update-form memory reference, or an 'x' for an indexed-form memory
reference.  However, these are really only useful in GCC internal code
generation.  In inline asm the operand of the memory constraint is
typically just a register containing the address, so 'U' and 'X' make
no sense.

This patch quietly accepts 'U' and 'X' in inline asm patterns, but
otherwise does nothing.  If we ever unexpectedly see a non-register,
we'll assert and sort it out afterwards.

I've added a new test for these constraints; the test case should be
used for other asm-constraints changes down the road.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217622 91177308-0d34-0410-b5e6-96231b3b80d8
Add missing colon to RUN line...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217623 91177308-0d34-0410-b5e6-96231b3b80d8
Misc cleanups to the FileSytem api.

The main difference is the removal of

std::error_code exists(const Twine &path, bool &result);

It was an horribly redundant interface since a file not existing is also a valid
error_code. Now we have an access function that returns just an error_code. This
is the only function that has to be implemented for Unix and Windows. The
functions can_write, exists and can_execute an now just wrappers.

One still has to be very careful using these function to avoid introducing
race conditions (Time of check to time of use).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217625 91177308-0d34-0410-b5e6-96231b3b80d8
Support: improve identify_magic to recognize COFF bigobj

identify_magic recognized a COFF bigobj as an import library file.
This patch fixes that.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217627 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the unused string section symbol parameter from DwarfFile::emitStrings

And since it /looked/ like the DwarfStrSectionSym was unused, I tried
removing it - but then it turned out that DwarfStringPool was
reconstructing the same label (and expecting it to have already been
emitted) and uses that.

So I kept it around, but wanted to pass it in to users - since it seemed
a bit silly for DwarfStringPool to have it passed in and returned but
itself have no use for it. The only two users don't handle strings in
both .dwo and .o files so they only ever need the one symbol - no need
to keep it (and have an unused symbol) in the DwarfStringPool used for
fission/.dwo.

Refactor a bunch of accelerator table usage to remove duplication so I
didn't have to touch 4-5 callers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217628 91177308-0d34-0410-b5e6-96231b3b80d8
[CodeGenPrepare] Teach the addressing mode matcher how to promote zext.
I.e., teach it about 'sext (zext a to ty) to ty2' => zext a to ty2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217629 91177308-0d34-0410-b5e6-96231b3b80d8
[C API] Make the 'lower switch' pass available via the C API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217630 91177308-0d34-0410-b5e6-96231b3b80d8
Support: Delete {aligned_,}{u,}{little,big}8_t

The byte has no endianness, so these types don't make sense.
uint8_t should be used instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217631 91177308-0d34-0410-b5e6-96231b3b80d8
Support: Use llvm::COFF::BigObjMagic

Use llvm::COFF::BigObjMagic insetad of the string literal.
Also checks the version number.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217633 91177308-0d34-0410-b5e6-96231b3b80d8
[MCJIT] Make sure we test ARM BR24 relocations with both internal and external
symbols.

Previously we have only been testing these relocations with external symbols.

<rdar://problem/18308413>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217635 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Fix off by 1 error in used register count

The register numbers start at 0, so if only 1 register
was used, this was reported as 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217636 91177308-0d34-0410-b5e6-96231b3b80d8