mmc: card: quirk: disable HPI for Kingston card

Certain Kingston eMMC 4.41 cards might get broken when HPI feature.
This quirk will disable the HPI feature for such buggy cards.

There are features depending on HPI, the change will disable them:
- BKOPS support
- stop transmission flow
- CACHE_CTRL

Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
Signed-off-by: LaboDJ <jacopolabardi@gmail.com>
drivers: usb: Use Android device as USB keyboard/mouse

Adapt to 3.4.y 8974/hammerhead
Base project: https://github.com/pelya/android-keyboard-gadget
Required app: https://play.google.com/store/apps/details?id=remote.hid.keyboard.client

Steps:
* Start ADB Debugging
* Start app
* Connect device to system via USB cable

All credits to @pelya for this sweet hack.

Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
Signed-off-by: LaboDJ <jacopolabardi@gmail.com>
Optimize build flags

Signed-off-by: LaboDJ <jacopolabardi@gmail.com>
msm: krait-regulator: handle efuse differences

Scaling factor version is valid for
- 8974 based devices when the version bits read 1
- 8974pro based devices when the version bits read 1 or 2
- 8084 based devices when the version bits read 0
- 8092 based devices when the version bits read 0

Moreover the three bit scaling factor data for
- 8974 based devices starts at bit 16
- 8974pro based devices starts at bit 16
- 8084 based devices starts at bit 14
- 8092 based devices starts at bit 14

Update the code to handle these differences.

[neo: Only required parts]

Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
Signed-off-by: LaboDJ <jacopolabardi@gmail.com>
msm: krait-regulator: fix unnecessary calls to switch to LDO

When asked to set a LDO voltage the driver rounds it up to
the nearest step value. However, when checking if the requested voltage
is already set it doesn't account for the rounding up.

Fix this by rounding up the requested value, which avoids
unnecessary calls to set the LDO voltage and switch to LDO.

Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
Signed-off-by: LaboDJ <jacopolabardi@gmail.com>
msm: acpuclock-krait: Program both high- and low-performance sources

The latest LDO/BHS switching sequence employed in the 8974
krait-regulator driver involves mandatory operations that cause
the CPUs to switch to the low-performance clock source when the
CPU is powered from the LDO, and to the high-performance clock
source when powered from the BHS.

This results in potential undervolting of the CPUs since the
acpuclock driver does not program the low-performance source,
and the clock source it selects be default is running at the
same speed as DDR (which can be very fast).

Fix this by programming both the high and low-performance clock
sources to be the same at all times.

CRs-Fixed: 538629
Change-Id: Iaa39cca9165b892e52acd8ec3aac5d0784112623
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: krait-regulator: enable support for KPSS v2 hardware

KPSS version 2.1 introduces a hardware sequencer which executes
the necessary steps to switch between BHS and LDO krait power modes.
The driver has to set the APC_PWR_GATE_MODE register to initiate a
switch between LDO and BHS Krait power modes. Modify the driver to
use this hardware sequencer.

Also, switch to the V2 SPM sequence with the delays added for
HW sequencer to idle.

Also, with the V2 sequences, it is expected that APC_PWR_GATE_CTL
register be configured once before using the APC_PWR_GATE_MODE register to
switch between LDO and BHS.

Update the code such that for secondary cpus APC_PWR_GATE_MODE is
written to after configuring APC_PWR_GATE_CTL in the
secondary_cpu_hs_init() function. Note that secondary_cpu_hs_init() is
guaranteed to run only once for each secondary cpu when that core is
brought up for the first time. Subsequent hotplug in/out of that core
do not take this code execution path.

For boot cpu, since it is up and running, its APC_PWR_GATE_CTL
should already be initialized. So for boot cpu configure its
APC_PWR_GATE_MODE register right at probe time. secondary_cpu_hs_init()
isn't invoked for boot cpu.

Change-Id: Ie5584c12f47283cad8834ccdb3d4d44c66305a22
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
msm: krait-regulator-pmic: Add krait-regulator-pmic driver

Read the register configurations of regulators in the gang and
bug if the gang is not setup correctly.

Importantly, fix the voltage overshoots observed during PFM-PWM
transitions by implementing the following steps.

PFM -> PWM
After the buck is set to PWM mode, wait 50uS and then set the PWM
current limit to 3.5A.

PWM -> PFM
After the buck is set to pfm mode, immediately lower the PWM current limit
to 2A (no delay required).

Change-Id: I15af09aaf8427e75253a4e12878ee1f0a1265454
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/Makefile
msm: krait-regulator: force BHS on offlined CPUs at boot

There could be regulator enable calls on offlined CPUs at boot time.
That leads to an issue where the driver calls smp functions on them
to switch ldo/bhs.

Set the force_bhs flags on offlined CPUs at boot to avoid this problem.

Change-Id: I9f5bccc89e59ef2da12670b921b98e02fb078acf
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
msm: krait-regulator: Add flag to disable LDO mode usage

Add a feature which allows to disable using LDO. When enabled, the
core continues to run from BHS possibly seeing a higher input voltage.
This may increase the leakage from the core but will not cause a
brownout.

Change-Id: I793af7a9eeddfd52f5fea9b4c59c774f0272f431
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
msm: krait-regulator: fix the cold boot sequence

One has to turn on BHS regardless of the kpss version. This gets
us to the expected APC_PWR_GATE_CONFIG register prior to enabling
sequencer.

Change-Id: I6c44f3e70b56211dae682c3b2740519f22f53f94
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
msm: Kconfig: Introduce a configuration option for krait regulators

Currently the krait-regulator driver is only compiled for 8974 based
devices. krait-regulator devices will be used in other MSMs.

Introduce a config option for the krait-regulator driver.

Change-Id: Ib4a636f940c6b4d22177edd86552399aaf5bd97c
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: LaboDJ <jacopolabardi@gmail.com>
ARM: dts: Enable additional GDSC collapse modes based on HW version

8974v2.2 supports additional collapse modes for Oxili, Venus,
and MDSS. Move the device-tree parameters that disable the modes
to version-specific files. Some MDSS collapse modes should still
remain disabled, even on v2.2.  All collapse modes are supported
on 8974Pro.

Change-Id: Ic9f1c057d16042d9a9c339dc5786cf35301169f0
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
ARM: dts: msm: Add krait-regulator-pmic devices to support the gang leader

Add entries to describe the gang leader and its associated peripherals.

On 8974v1, 8974v2, and 8974pro-ab based devices, PMIC 8841 SMPS 5
regulator is the gang leader.

On 8974pro-ac PMIC 8084 SMPS 8 regulator is the gang leader.

Change-Id: I67e2aea81743ab1f463cca8961d7700e48dc6283
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
ARM: dts: msm: correct tz-usage-tables in DTSI files.

Update TZ usage table to match expected values in TZ.  Incorrect values
caused secure buffers to be hinted incorrectly to TZ.

Signed-off-by: Cullum Baldwin <cullumb@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm: krait-regulator-pmic: account for PWM_CL register security

The PWM_CL register is secure i.e. driver has to write 0xA5 to 0XD0
register to allow updates to PWM_CL register.

Fix it.

Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>