utils: add helpers for finding verilator and VERILATOR_ROOT

find_verilator code is factored out from verilator.py.
get_verilator_root relies on the fact that verilator will print
the hardcoded value for VERILATOR_ROOT when fed '-V' as an
argument.
verilator: use find_verilator() helper
sections: use get_verilator_root to obtain VERILATOR_ROOT
fusesoc.in: Change error string formatting

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
fusesoc.in: catch exception on configure and add_cores_root

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
provider: raise exception on unknown/missing provider

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
provider: url/opencores raise exception on _checkout errors

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Improve error output printing style

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
sections: add src_root to verilator build include

This solves a problem with inter-core dependencies,
where header files have to be shared between cores.
Doing it this way, cores can include files from other cores by:
#include <other-core/file.h>

The alternative would be for each core to export an include
path, but this might result in namespace clashes between include
files from different cores. Plus, it would be messier to
implement in fusesoc.
verilator: use --start-group/--end-group on archives only

I don't really have an excellent rational behind this,
other than it fixes a real-world problem I had when compiling
several cores depending on each other, and it doesn't seem to
break anything else.
sections: add CPP source_type
Move section to a separate python module

We anticipate that the number of sections will grow, so this is a
good time to put it in a separate module
Add section factory and use it in core.py
class Section: Add export function

This defines an export function that can be used by all subclasses
by defining all exportable files as a list called self.export_files.

Note: This is yet another patch that does not add multiple inheritance
backend: pass args to backend build functions
backend: add support for Xilinx ISE
VerilatorSection: add export() method

This add an export() method to VerilatorSection, with the purpose
of exporting a list of files to be used in core.py.
core.py is also updated to make use of this method.
quartus: add support for qsys generation

When the (new) 'qsys_files' entry under the 'quartus' section is
present, a shell script is created with the necessary commands
generate a system described in a .qsys file.
The approach with first creating a shell script and then
executing that, instead of executing the commands directly from
fusesoc was chosen to keep the build directory still completely
independent from fusesoc once generated.
ise: use jtagclk

Needs investigation what the different clocks does...
And possibly generate several .bit files for different clocks.