msm: mhl: sii8334: handle MHL discovery failure cases

Reset mhl mode on disconnect and suspend to avoid discovery wait
timeout in case connect interrupt is received before start of wait.

Free IRQ on suspend and reconfigure in discovery to avoid unnecessary
wakups and suspends during PM shutdown.

Notify USB in case discovery is failed and on suspend to take over
the control.

CRs-Fixed: 579997
Change-Id: If0747b067d53563c3eb380e80be1254d38b140d6
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
msm: mdss: optimize MDP pipes cleanup

There are cases where pipe cleanup can happen without display commit.
This means that the pipe was never programmed to hardware, in these
cases the pipe can be cleaned up without the need of display commit
cycle to happen. Also there is no need to access hardware to release
resources such as SMPs since they have not been programmed yet.

Change-Id: I57a46471dc1fba4e45e55c3543940ba4fba0540a
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdss_mdp_pipe.c
msm: mdss: implement overlay prepare ioctl

Overlay prepare will allow a full frame with multiple overlays to be
configured at once and perform frame level checks before being pushed to
display. This function guarantees that if the call is successful, the
frame can be displayed successfully on the screen when display commit is
called.

Change-Id: I276b6fe3e0a872a2e93170f3cea1002d3ce0dac9
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Anusha Koduru <kanusha@codeaurora.org>

Conflicts:
	include/linux/msm_mdp.h
msm: mdss: Move bus scale table implementation to device-tree

Bus scale table is chip-set dependent where number of paths per
bandwidth use-case can differ chip-set to chip-set. Current
implementation has a static table where it supports only one path per
use-case. Expand MDSS bus scaling implementation to accommodate
chip-sets where more than one path per use-case, i.e. apq8084, is
possible and move table initialization to device-tree so that every
chip-set configures its own table.

Conflicts:

	Documentation/devicetree/bindings/fb/mdss-mdp.txt
	arch/arm/boot/dts/apq8084-mdss.dtsi
	arch/arm/boot/dts/msm8226-mdss.dtsi
	arch/arm/boot/dts/msm8974-mdss.dtsi
	drivers/video/msm/mdss/mdss.h
	drivers/video/msm/mdss/mdss_mdp.c

Change-Id: Ia6f76654d129fe0ec1a7124aa87b16f96167fe84
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
msm: mdss: move mdss fudge factors to device-tree

MDSS has a common driver for multiple chip-sets. Each of these chip-sets
can have their own fudge factors for calculations of resource demand.
Move these pre-defined fudge factors to device-tree since they are
platform dependent.

Conflicts:

	Documentation/devicetree/bindings/fb/mdss-mdp.txt
	arch/arm/boot/dts/msmsamarium-mdss.dtsi
	drivers/video/msm/mdss/mdss.h

Change-Id: Ia558a2ad0a096b49cdabf41dd25cf30c843149c4
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
mdp: mdss: Tune bandwidth and clock based on ROI

Calculate bandwidth and MDP clock requirement considering
the ROI submitted for a frame. When doing partial frame update
for smart panels, the data actually fetched for a pipe is not
always the full resolution of the buffer programmed. Use the
ROI passed to find out the region of fetching and calculate the
bandwidth and clock values accordingly.

Change-Id: I01f24f8fd9a42a2c4d705b8eb0a7658e79884175
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
msm: mdss: Add support for macro tile formats

MDP now supports tile formats on APQ8084. Macro tile formats
are aligned with number of memory banks and access channels to
improve performance.

Conflicts:

	Documentation/devicetree/bindings/fb/mdss-mdp.txt
	drivers/video/msm/mdss/mdss_mdp_pipe.c
	include/uapi/linux/msm_mdp.h

Change-Id: Ie566cc12b38f81d111f378f19883433bcc71fa48
Signed-off-by: Shalabh Jain <shalabhj@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdss_mdp_pipe.c
msm: mdss: calculate mdp clk requirement of each pipe with the fudge factor

Currently the mdp clk margin is added for the final calculated max of
all individual pipe clk requirements to avoid underruns. When this
final rate is greater than the max rate that h/w can support, pipe
decimation mode may not be enabled to avoid underruns. So, move this
margin calculation into each pipe clk so that when any individual pipe
has higher clk rate than the max, pipe decimation can be enabled.

CRs-fixed: 538803
Change-Id: Ia4dc500cfc27e7e4d08f03066b511ed3e4ae4664
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
msm: mdss: refactor performance calculations

Current logic could potentially lead to drop in performance (and
underflow) when multiple panels are there and both are updating mixer
configuration independently, as we may end up raising bus bandwidth for
another panel which may not be ready just yet. This is addressed by
updating performance configuration values until it's ready to switch
rather than updating values and performing these later (other panel
update could come in between).

Change-Id: I247ef0cd3e0616de3e5ddd9599233af570e422a5
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdss_mdp_ctl.c
msm: mdss: add mdp overlap and prefill bandwidth calculations

This patch implements a set of new equations proposed by h/w team to
calculate mdp bandwidth. MDP has bandwidth requests during both
blanking and active periods. During blanking area, mdp needs to fill
its internal buffers, such as latency buffer, outstanding buffer,
pingpong buffer, etc. This bandwidth is called prefill bandwidth and
it is determined by the total amount of bytes of buffers to be filled
and the total amount of blanking time available. The bandwidth for the
active peroid is called overlap bandwidth which is the max bandwidth
request of all overlapped regions. The final vote from mdp would be
the worst case of prefill bandwidth and overlap bandwidth.

Change-Id: Ib83caf6a3e15c33a2cd71d14e8413b1d9049de29
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdss_mdp_ctl.c
msm: mdss: support mdp prefill bandwith for multiple platforms

To calculate mdp prefill bandwidth, mdp driver needs to get h/w
dependent buffer constants from device tree. Also add h/w feature
dependent logic.

Conflicts:

	drivers/video/msm/mdss/mdss.h

Change-Id: I8d56ec502a6fd56eaae5b65a326ef966be46f14b
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
msm: mdss: reduce mdp prefill bandwidth vote for command mode panel

The current result of mdp prefill bandwidth calculation for command
mode is larger than what is actually needed for many use cases. This
is due to the fact that for command mode panels during prefill time,
there are less buffer prefill requirement or time constraint than that
of video panels. This patch makes adjustment accordingly based on the
updated equations by h/w team.

Change-Id: I06935a29d771202b3f8dc2c62cf948a8ecc81481
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
msm: mdss: calculate prefill bandwidth using the worst case vbp

The blanking period of a panel is determined by vbp factor: vertical
back porch plus vsync pulse width. The larger vbp, the larger blanking
time, and the smaller prefill bandwidth request. When two or more
types of interfaces/panels are involved, although each panel has its
own vbp, there is an option to calculate the prefill bandwidth for
each panel with the worst case vbp of all panels. This way there is no
need to increase fudge factor to avoid underruns.

Change-Id: I60dda6ad41bbb353c58ef93cf97787c4da3929dc
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
msm: mdss: Fix for bus bandwidth issue

Fixing possible large values handling.

Change-Id: Id9e4aafa2a922c2c90def037b110826344487fcd
Signed-off-by: Radhika Ranjan Soni <rrsoni@codeaurora.org>
msm: mdss: add tile format condition for prefill bytes calculation

Latency buffer requires more lines to be prefilled for use cases that
supports tile format.

Change-Id: I552bade677822d47cdd5b43c01f795552e94b406
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
msm: mdss: update latency buffer bytes calculation for prefill bandwidth

This is a s/w change to reflect the new h/w update of latency buffer
byte calculation for prefill bandwidth. Previously this number of
latency buffer bytes is the amount of allocated smp bytes, however,
for some use cases this doesn't not match the bandwidth equation
result. So for the purpose of matching mdp prefill bandwidth
equations, a standalone calculation is needed.

Change-Id: Ic74599d2c2bfe9610ebc22dee137a0df7171dcb5
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
msm: mdss: add bandwidth check function

Add function which calculates the bandwidth that would be required by
MDP to display the frame. If the bandwidth is over the defined limits,
an error is returned which means the configuration is not acceptable and
may lead to display underruns.

Change-Id: I991ac458d347487c5c634d271814222aa661fd58
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Anusha Koduru <kanusha@codeaurora.org>
video: msm: Remove some cruft

Change-Id: Ie58a051b7836e5f6a7178034cd65f92c148b9bd9
msm: mdss: set pipe to solid fill when releasing it

There are cases where pipe can remain active for additional vsync after
unstaging from mixer, if this ever happens it will keep fetching from
memory. In order to avoid this, we can setup the pipe in solid fill mode
so there is no memory access after pipe is released by software and
avoid potential iommu page fault or underrun since pipe is no longer
considered for bandwidth calculations.

Change-Id: I4b5a5deda8c854c504ef523df434509fa5567186
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
msm: mdss: properly handle panel on and off

There is some condition that panel off will be called multiple times.
In this case, it was blindly free the gpios that were already released.
This is adding the check to handle this condition.

Change-Id: I0140872be1255fe00ed5abd164a246fa57b2a245
Signed-off-by: Xiaoming Zhou <zhoux@codeaurora.org>