axi_ifc: reader/writer modports
axi_hp_dma_reader/writer: 64bit high performance dma (first cut)

These send back-to-back bursts (always 16 beats), but handle
the address/data/ack streams separately to attempt to minimize
cycles lost on state transitions and allow interconnects to
have as much information as possible (ie, that this read will
be followed by the next read, etc etc).
zynq wrappers exposing 1/4 high performance axi ports
zybo-axi-test: experiments with hp axi ports