Merge pull request #23 from hansiglaser/master

new %s: add sub-modules to selection
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
Merge branch 'master' of github.com:cliffordwolf/yosys
Added support for %m selection op
Added i:, o:, and x: selection pattern
Added support for s: select expressions (wire width)
Added design -stash/-copy-from/-copy-to
Added copy command
Added "retime" to standard ABC recipes
Updated ABC to rev 10cc13a2a0f1
Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim failed)
Fixed gcc compiler warnings with release build
Fixed use of "cmd_error" in passes/cmds/design.cc
Added echo command
Re-enabled abc "retime" after sorting yout the yosys-bigsim problem
Stronger checking of internal cells
Added $slice and $concat cell types
Added $slice and $concat to CellTypes list
Added log_header() to splitnets
Added splice command