mmc: sdhci-msm: enable async suspend

This is aimed to reduce the suspend time of sdhci-msm device.
The suspend of this device would be carried out in a separate
thread and other devices may suspend concurrently. This is
required since the mmc sub-system contributes to the major
chunk of suspend latency.

CRs-fixed: 634333
Change-Id: I7bdead2deacd96aec5201d82b143b07c470b3892
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
TTY: msm_smd_tty: Fix simultaneous open/close race condition

smd_tty_close currently has a variable that depends on a race
condition with tty_port_open. This causes a null-pointer dereference
when the same port is simultaneously being opened/closed.

Use data from a static array instead of the variable to eliminate
the race condition.

CRs-Fixed: 624398
Change-Id: Ie55d37feaadd3a15f64e18501cd3af19145dbc8e
Signed-off-by: Steven Cahail <scahail@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
usb: gadget: Fix response available notify count usage

The outstanding responses are purged and notify count is reset
during bus suspend. But the notify interrupt endpoint is not flushed.
If a request is pending with the controller, It gets finished during
resume and the notify count is decremented in the completion handler.
As the notify count is reset during the suspend its become negative now.
As the counter is not zero, interrupt notifications are queued even
though there are no responses. This is leading to watchdog bark due to
an error print messages.

Flush the notify endpoint before resetting the notify counter during
suspend. As we are modifying notify counter under spin lock, atomic
variable is not required. Ensure that notify counter never
becomes negative.

CRs-Fixed: 607029
Change-Id: I78cb7a585c1c2b527ca6b46bc99e7db8067ee21a
Signed-off-by: ChandanaKishori Chiluveru <cchilu@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
crypto: msm: optimize ce bandwith scaling

Encryption processing at qcrypto driver includes three main steps:
set ce high bandwidth and enable ce clock in cra_init, then send
encrytion request, and at last set ce low bandwidth and disable
clock in cra_exit. This process is fine for the use case where
there are lots of requests between cra_init and cra_exit, but will
introduce large overhead for mmc layer disk encryption as it calls
cra_init, queue request and cra_exit for every encryption request.

It is not necessary to set low bandwidth and disable clock for every
encrypt request when it is completed. So we delay these scaling down
tasks for a while, and just scale down the last request when timer
expires so as to amortize and decrease the overhead.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
crypto: msm: fix issues in ce clock disable processing

In the situation of more than one requests, the ce clock may get
errorneously disabled even when there are active requests. The
scaling operation is then modified to fix the problem and ensure
all requests are completed when disable the clock. We also clean
up the related codes.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
crypto: msm: multiple qcrypto support

This patch provides support for multiple qcrypto devices
with the qcrypto driver.

Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
crypto: msm: fix hmac hashing issues with various key size

hmac-sha1 and hamc-sha256 have variable mac key up to a block size.
If user provides a key that is less than the block size, the
key should be padded with zero to the block size before it is
given to the hw.

This padding was not done properly in the driver.
When switch engine between ahash hmac(sha1), hmac(sha256),
and ipsec, problem may happen. ipsec takes 20 bytes of key.
The generated digested data is wrong, even though everything looks
fine from driver. ipsec may fail.

Furthermore, this patch cleanup the driver to do proper setup of
hardware to use hw key or pipe key.

Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
crypto: msm: fix hmac ahashing issues with simultaneous multiple requests.

 This patch fixes two issues. One issue is to do with simultaneous requests
 of a ahash tfm. The other issue is to do with ahash import, and export
 functions.

 Agent issues chain of requests in sequence of init, followed
 by multiple updates, and final to the crypto driver for the hashing of a
 buffer. Each request can be asynchrounous. After a request is complete,
 the next one in the sequence is issued.

 Multiple simultaneous async requests can be issued to the driver
 for the same tfm if they are for independent hashing.

 In the driver, the state variables such as trailing buffer, first
 block, last block are maintained in the driver. The
 state variables are maintained in the request context, instead of
 tfm context. Otherwise, simultaneous async requests can
 confuse each other. This patch moves those variables out of
 tfm context to request context to fix this issue.

 Agent above the driver can import/export ahash state of a request. This
 patch fixes a few issues in the driver to support import/export.
 First issue, the byte count returned from hw for hmac has 64 bytes of
 padding on the first request to the hardware. In the import/export this
 special case needs to be accomodated.

 The 2nd issue is the state buffer is only updated after hardware operation
 complete. For the first, data being accumulated in the trailing buffer,
 and if request has not ever issued to the hw, when import function comes,
 the trailing data needs to be exported. This patch uses trailing
 buffer directly as state buffer variable for import and export.
 The context update functions after hareware request complete are not
 necessary and they are removed. The last issue is to do with state
 variable count. It was not initialized. That may cause hashing generated
 wrong  digest after export and import.

Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
crypto: msm: add pm wakeup support for qcrypto driver

Add support for holding system from suspending while an operation
is in progress (when clks are enabled).  This is done by invoking
pm_stay_awake before enabling clks (when a crypto operation is
initiated) and invoking pm_relax when crypto operation is done.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
crypto: msm: Rename and register crypto algorithms

Add optional crypto algorithm flags to indicates if to use SW crypto
algorithms instead of HW algorithms. Based on it, we then rename and
register crypto algorithms to be qualcomm specific to prevent clashing
with the default SW implementation of the algorithms used by dm_crypt
module. (used for disk encryption).

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
crypto: msm: Add basic suspend resume functionality

If ce clock is not disabled in suspend state, memory may be corrupted
and device can not wake up. We add an optional flag "clk_mgmt_sus_res"
for qcrypto driver. This flag indicates if the ce clocks need to be
disabled in suspend function and enabled in resume function of qcrypto
driver. When the flag is set, we disable the clocks that are not disabled
in suspend function and re-enable them again in resume function.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
crypto: msm: enable rfc4309(ccm(aes)) algorithm

This patch enables rfc4309(ccm(aes)) algorithm. Further more, it fixes
an issues with ccm.  According to RFC3610, associate
data is optional. The assocaite data length can be 0 as shown in
testmgr ccm rfc4309 test vectors. The driver did not take this zero
length of  associate data situation into account. And the corresponding
test vectors in testmgr may fail.

Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Niranjana Vishwanathapura <nvishwan@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
crypto: msm: Add support for multiple qcrypto devices

Expose APIs to enable qcrypto client to select any specific qcrypto
instance.

Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: dts: msm: Add support for ce-device number in crypto driver

Add an entry for ce-device in qcedev and qcrypto device nodes.

Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: fix executability of CMA mappings

The CMA region was being marked executable:

0xdc04e000-0xdc050000           8K     RW x      MEM/CACHED/WBRA
0xdc060000-0xdc100000         640K     RW x      MEM/CACHED/WBRA
0xdc4f5000-0xdc500000          44K     RW x      MEM/CACHED/WBRA
0xdcce9000-0xe0000000       52316K     RW x      MEM/CACHED/WBRA

This is mainly due to the badly worded MT_MEMORY_DMA_READY symbol, but
there are also a few other places in dma-mapping which should be
corrected to use the right constant.  Fix all these places:

0xdc04e000-0xdc050000           8K     RW NX     MEM/CACHED/WBRA
0xdc060000-0xdc100000         640K     RW NX     MEM/CACHED/WBRA
0xdc280000-0xdc300000         512K     RW NX     MEM/CACHED/WBRA
0xdc6fc000-0xe0000000       58384K     RW NX     MEM/CACHED/WBRA

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[lauraa@codeaurora.org: Context fixups due to __dma_remap signature change]
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: dma-mapping: don't allow DMA mappings to be marked executable

DMA mapping permissions were being derived from pgprot_kernel directly
without using PAGE_KERNEL.  This causes them to be marked with executable
permission, which is not what we want.  Fix this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[lauraa@codeaurora.org: dropped functions not in older builds]
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
ksm: Provide support to use deferred timers for scanner thread

KSM thread to scan pages is getting schedule on definite timeout.
That wakes up CPU from idle state and hence may affect the power
consumption. Provide an optional support to use deferred timer
which suites low-power use-cases.

To enable deferred timers,
$ echo 1 > /sys/kernel/mm/ksm/deferred_timer

Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: vidc: Add support for H.264 LEVEL 5.2

For high resolutions and bit rates, H.264 spec
defined new level. This change adds support to
pass LEVEL 5.2 to FW.

Signed-off-by: Praneeth Paladugu <ppaladug@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: vidc: update hevc codec macro

Firmware expects hevc codec macro value
of 0x00002000.

Signed-off-by: Arun Menon <avmenon@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: vidc: add hevc hybrid driver support

Changes to support hybrid hevc decoder in
v4l2 video driver. Dsp only hevc decoder does not
have mips to handle high resolution (1080p) and
software only solution has thermal/power impact.
Hybrid hevc decoder will have lower power numbers and
better performance for high resolution (1080p).

Signed-off-by: Maheshwar Ajja <majja@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>