Added a register between the data read from the DDR3 and the async RX FIFO
(this was done for signals app_rd_data and app_rd_data_valid). Numerous
timing violations were observed between this logic path, this is an
attempt to correct this.
Added an explicit latency of 1 to the Relational block - According to
the Mail archive of the CASPER Wiki ("Strange problem in the FFT") -
The default latency of this block is 0 for System Generator 14.x. This
causes channel reordering problems since this is suppose to be a latency
of 1.