Changes to matlab peripheral file generator

- Added a yaml_sanitize function to explicitly stringify
outputs if they have colons in them. (e.g. shared bram initial
values, which often have fields like [0:128]).
TODO: investigate evaluating the fields in matlab.

- ignore gateway blocks in a simulink design if they're in a subsystem with
a xilinx ignore-subsystem block. The shared bram has a simulation
subsystem like this. Having done this, it turns out vivados
system generator doesn't support the ignore subsystem block
anymore anyway, so we'll need another way to add a simulation
model to the bram (and probably other blocks)
Removed simulation subsystem from shared bram

For compatiblility with vivado's sysgen, which
doesn't support the ignore subsytem block that
the shared bram uses
Shared bram yellow block.

Support the register core/primitive output options.
Added ClockConstraint class

for adding clock constraints, obviously.
Added ClockConstraint to backend constraint flow
Added some shared brams to the adc test model
Finishing the adc16

Various fixes to erroneous pinouts.
Seems to compile OK -- still needs a more
thorough check of the warning log to check for any
badness.