Merge commit '0f5f6bbc3a0bb125875f28ad61584001989a7f10' of git://codeaurora.org/quic/la/platform/art into kk4.4

Conflicts:
	runtime/jni_internal.cc
	runtime/native/dalvik_system_Zygote.cc
	runtime/oat.cc
	runtime/stack.h
	runtime/thread.cc
Inline codegen for long-to-double on ARM.

Change-Id: I4fc443c1b942a2231d680fc2c7a1530c86104584
Clean up usage of carry flag condition codes.

On X86, kCondUlt and kCondUge are bound to CS and CC,
respectively, while on ARM it's the other way around. The
explicit binding in ConditionCode was wrong and misleading
and could lead to subtle bugs. Therefore, we detach those
constants and clean up usage. The CS and CC conditions are
now effectively unused but we keep them around as they may
eventually be useful.

And some minor cleanup and comments.

Change-Id: Ic5ed81d86b6c7f9392dd8fe9474b3ff718fee595
ARM: Remove duplicated instructions; add vcvt, vmla, vmls disassembler.

Remove kThumb2VcvtID in the assembler which was duplicated.
Add vcvt, vmla, vmls in the disassembler.

Change-Id: I14cc39375c922c9917274d8dcfcb515e888fdf26
ARM: Inline codegen for long-to-float on ARM.

long-to-double-to-float using vfp instructions should be faster than the
function provided by toolchain.

Change-Id: I7ff809bca6665f0c1a0d7e6db98d570ce86b7c66
Faster AssembleLIR for ARM.

This also reduces sizeof(LIR) by 4 bytes (32-bit builds).

Change-Id: I0cb81f9bf098dfc50050d5bc705c171af26464ce
Tidy up memory barriers.

Change-Id: I937ea93e6df1835ecfe2d4bb7d84c24fe7fc097b
Add conditional move support to x86 and allow GenMinMax to use it

X86 supports conditional moves which is useful for reducing branchiness.
This patch adds support to the x86 backend to generate conditional reg
to reg operations. Both encoder and decoder support was added for cmov.

The x86 version of GenMinMax used for generating inlined version Math.min/max
has been updated to make use of the conditional move support.

Change-Id: I92c5428e40aa8ff88bd3071619957ac3130efae7
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Fix -O0 builds.

Use snprintf rather than sprintf to avoid Werror failures.
Work around an annotalysis bug when compiling -O0.

Change-Id: Ie7e0a70dbceea5fa85f98262b91bcdbd74fdef1c
Move fused cmp branch ccode to MIR::meta.

This a small refactoring towards removing the large
DecodedInstruction from the MIR class.

Change-Id: I10f9ed5eaac42511d864c71d20a8ff6360292cec
Remove non-existent ARM insn kThumb2SubsRRI12.

For kOpSub/kOpAdd, prefer modified immediate encodings
because they set flags.

Change-Id: I41dcd2d43ba1e62120c99eaf9106edc61c41e157
Disassemble Thumb2 shifts and more VFP instructions.

Disassemble Thumb2 instructions LSL, LSR, ASR, ROR and VFP
instructions VABS, VADD, VSUB, VMOV, VMUL, VNMUL, VDIV.

Clean up disassembly of VCMP, VCMPE, VNEG and VSQRT. These
could have been erroneously used for other insns (VSQRT for
VMOV was encountered) and one VSQRT branch was unreachable.

Remove duplicate VMOV opcodes from compiler.

Change-Id: I160a1e3e4b6eabb6a5101ce348ffd49c0573257d
Re-apply: Initial check-in of an optimizing compiler.

The classes and the names are very much inspired by V8/Dart.
It currently only supports the RETURN_VOID dex instruction,
and there is a pretty printer to check if the building of the
graph is correct.

Change-Id: I28e125dfee86ae6ec9b3fec6aa1859523b92a893
Add conditional branches, and build dominator tree.

Change-Id: I4b151a07b72692961235a1419b54b6b45cf54e63
Add codegen support to the optimizing compiler.

Change-Id: I9aae76908ff1d6e64fb71a6718fc1426b67a5c28

Conflicts:
	build/Android.gtest.mk
Add register support to the optimizing compiler.

Also make if take an input and build the use list for instructions.

Change-Id: I1938cee7dce5bd4c66b259fa2b431d2c79b3cf82
Fix lint errors.

Change-Id: Ibefa43522ec68ed2a13bd034005d6f424e92957c
More code generation for the optimizing compiler.

- Add HReturn instruction
- Generate code for locals/if/return
- Setup infrastructure for register allocation. Currently
  emulate a stack.

Change-Id: Ib28c2dba80f6c526177ed9a7b09c0689ac8122fb
Fix non-{arm, x86} builds.

Change-Id: If4c13775f8e1fd0fd26b4a731f3011c77b0bfed1
Use imprecise constants at compilation time.

During veriifcation, we create constant types for the following instructions:
const/4, const/16, const and const/high16. We used to create "precise" constant
types for each constant we process in the method being verified. Though precise
constants are only useful for deoptimization which happens at runtime.

This CL now creates "imprecise" constant types at compilation time. Since it
reduces the number of constant types we create during verification, it should
also reduce the amount of time spent in verification at compilation time.

Bug: 12167380
Bug: 12126841
Change-Id: I70522c4133a74a533fc2d2cb8d4f49888e590828