ISE: Fix project paths

The ISE project cannot open as the HDL files have moved since it was
last used. Fix the paths so that it works again.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Add UART to design

This uses the Exar XR21V141x UART to USB bridge that is present on the
Digilent Atlys development board.

TODO: The added verilog files need licence information
Add debug module

The debug module collects counters from the system for debugging.
The following counters will be supported:

 - in frame rate
 - frame rate
 - frame rate write time
 - processing time
 - frame drop count
 - f data (?)

TODO: Add units, and how to access these counters
Connect counters to system

This connects the debug counters to the appropriate points in the
system.
Commit misc Xilinx ISE XML changes

Unknown if they are required, but they were part of the previous
changes. Add them as part of a separate commit to make the code changes
easier to review.
Commit misc encoder change

TODO: Must ask Ajit about this. Looks like a leftover test?