Correct handling of FEATURE_MULTICORE
DCache: Coherency WIP

This is a big blob that adds coherency via the snoop port. It does not
yet work, I think as the assumptions about the cpu protocol and the
overlay of snooping and the normal cache operation are not correct. I
assumed that the operation can be overlayed and that it is sufficient
to backpressure the LSU via the snoop_read_tagmem (tag read overlay)
and snoop_hit (tag write overlay) signals, but that is not the case or
wrongly implemented.

The cache has the option to have a duplicate tag memory for snooping,
which will significantly improve performance over the other
alternative where the normal tag memory is used. For the moment I work
on getting the separate cache running and try to work out the cpu
interface, which I started summarizing on top of the cache as
documentation.
Fix typo from old naming (I called them snoop_check and snoop_access before instead of snoop_read and snoop_check)
DCache: Bugfix when using snoop tag memory

We should also write back the correct tags and not the ones from the
other tag memory..
LSU: Fix bug with lwa and snoop of same address

When a snoop event occurs parallel to the lwa completion, the swa
should fail. This is enabled by this patch that essentially simply
changes the order of checking.
Merge branch 'wip_coherency' of git://github.com/wallento/mor1kx into multicore

Conflicts:
	rtl/verilog/mor1kx_lsu_cappuccino.v