move findOrdering & findGraphDims from Module to Backend
use nodes instead of mods for code generation in VerilogBackend
reimplement findOrdering and use Driver.orderedNodes instead of omods for code generation in CppBackend
execuate addBindings only in the Verilog Backend
fix sortedComps and clean up
Merge branch 'master' of github.com:ucb-bar/chisel