mmu: fix priv signal

The kernel access bit was wrong (19 instead of 31) and the
check has to be against the present PSW_UC bit, not the one from
previous clock cycle.
propagate exceptions from fetch stage
generate dtlb_priv exceptions

and add missing dtlb_write output
implement trap instruction/exception
add support for tbwr instruction
avoid interrupts right after jumps
lsu: flush load/store ops in mem_stage
use `ECO32F_EID_PRIVILEGED_ADDR for tlb priv exceptions
make sure refill_cnt = 0 on all other state changes than refill

this is necessary, since the burst mode is muxed on this signal
write tlb_entry_hi and tlb_bad_address on itlb exceptions