WIP: xa: handle solid-fill src/mask
WIP: xa: remove unneeded args
WIP: xa: scissor to help tilers..
WIP: xa: reuse surfaces

Otherwise it will trick the gallium driver into thinking that the render
target has actually changed (due to different pipe_surface pointing to
same underlying pipe_resource).  This is really badness for tiling GPUs
like adreno.
WIP: freedreno/a3xx: missing wfi

RB_FRAME_BUFFER_DIMENSION is not a banked context register.
WIP: freedreno/a3xx: little extra debug
WIP: freedreno/a3xx/compiler: avoid negative register ids

In some cases, we need a register to be assigned up to three components
before the base.  Since we can't have negative register #'s, just shift
everything up.  May increase register usage for trivial shaders, but I
don't think we are shader limited in those cases.  A proper solution is
going to require a better register assignment algorithm (which is on the
TODO list).