msm: pm-8x60: Use dma_alloc_coherent for the saved region

dma_alloc_coherent is the linux standard way of allocating coherent
(i.e. uncached) memory. This API provides more guarantess than the
custom allocate_contiguous_ebi function, including the ability to
specify allocations from the lower 4G of memory. Switch to this API
for allocation of uncached memory. Because using dma_alloc_coherent
may have other setup involved, switch the setup function to be a
later initcall as well (from core_initcall to arch_initcall).

Change-Id: I96ea4575e5ee82ccbf7e691ba75ea1414dc6d81a
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Revert "msm: pm-8x60: Add PNOC request to prevent PNOC clk gating"

This reverts commit 9b186afca6c206ef1e74c138a10b75bdab4ba422.

Change-Id: Ifb0e0af69f6e63cae74ba2c50cb5d126257bc43d
Signed-off-by: Badhri Jagan Sridharan <badhris@codeaurora.org>
msm: pm-8x60: Update the identity mapping for LPAE

The pm code uses a known stable page table with an identity mapping
for coming in and out of power collapse. This table currently assumes
a standard two level page table. This is incompatible with the new
format for LPAE. Update the code to handle both the LPAE and non-LPAE
page tables for power collapse.

Change-Id: I58097744134207fac49d7ab2147ba34f2f244a94
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
msm:pm-8x60: Do not generate access flag faults for the kernel mappings

The pgd mapping (msm_pm_pc_pgd) generates Access flag fault whenever
this entry is read into the TLB for the first time. Add this flag to
the pgd mapping such that when the fault occurs, software resets the
Access flag to 1 in the translation table entry that caused the fault.
This prevents the fault from occurring the next time that memory
location is accessed.

Change-Id: I8d2ecc4d4005955ddeeaf3953ca1c445163b694c
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
msm: mpm: Use clock API to prevent XO shutdown

When the active interrupts cannot be monitored by MPM during system
sleep modes, use linux clock APIs to vote against XO shutdown. Earlier
mpm driver relies on lpm resoures to overwrite the clock votes based on
enabled interrupts. This change decouples the MPM driver from the
lpm resources and thereby removing the dependency on RPM driver.

Change-Id: Ica5409ebb6744998303d84867f9b6d0243664b7e
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm-8x60: Register sleep status driver before regulator

During hotplug, drivers wait for core to be power collapsed to turn off
the resources used by a core in CPU_DEAD notification. The kernel
thermal module which hotplugs the core in certain conditions is
registered in the arch_initcall(). To ensure that the CPU_DEAD waits for
sleep status to be set during hotplug, register the cpu sleep status
driver before the regulator driver.

To this effect, the sleep status driver is no longer made a child device
for pm-8x60 device.

Change-Id: I772521f4b3cd18e367aa44a41d60ef9735c99ef9
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: lpm: Alter the voting mechanism for lpm drivers

Currently the power management drivers monitor the sleep votes received
for certain system wide resources such as system clock and digital voltage
rail. By knowing the sleep vote and the available sleep time , latency
requests the low power management drivers (lpm_resources module) can alter
the sleep votes for those resources during RPM notified sleep modes.

Changing this method because this method requires a new low power level be
added for each combination of the system wide resources being monitored
and that each level be characterized (latency, power etc), this method is
not very scalable as the number of system resources being monitored by the
low power management driver increases. But most of all the decisions on
whether there is enough sleep time to enter these system wide sleep modes
(residency decisions) need to be made at RPM.

This change will remove the lpm_resources module altogether and remove all
low power levels beyond those pertaining L2 cache at lpm_levels.

CRs-Fixed: 490824
Change-Id: I255b696851074dcf7bed40b648c0eb3c5c4d0d6d
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
msm: lpm_levels: Adjust latency for Multi core cases

In multi core cases for several cores going in and out of power collapse
the warmboot is serialized at Trust Zone, which means the exit latency
will scale based on the number of cores exiting power collapse.

Adjust for this when chosing a low power mode based on the number of online
cpus.

Change-Id: I4fe137a1bf8596b7da7990845b18ceb8f3d529da
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
msm: spm: add intermediate LPM mode for L2 PC

Currently when the core decide to enter into "PC + L2 PC"
LPM mode it informs to RPM and there is a chance of
system can enter into either XO or VDDmin. But this LPM
mode take longer time to enter and exit. Because of this
limitation some of the usecases where there is a less
latency APPS proc stays at lower LPM level (i.e GDFS) and
causing more power consumption. To address this issue adding
an intermediate LPM mode where L2 goes to PC but not inform
to RPM.

CRs-fixed: 552743
Change-Id: I321ff260d5baf8ac44917d67e9c9dfd260c8d5ca
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
msm: idle-v7: flush non secure L1 cache lines for l2 GDHS LPM mode

It is LPM driver(HLOS) responsiblity to flush non secure lines of
L1 cache when the core decide to enter a LPM mode where core get
powered off. But current code is not flushing the non secure lines
of L1 cache when the core decide to enter into L2 GDHS LPM mode.
This change addresses the flushing of non secure lines of L1 cache.

CRs-fixed: 555905
Change-Id: I721947386091875994bcb71bd8b9b9b793a72349
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>