Fixed bug in exception code logic in COP0.
Added support for HW interrupts in the CPU. Not tested yet!
Added debug registers in the SW simulator to support testing the HW interrupts.
Also reordered a bit the debug registers in the address map.
Added support in the core TB to test the HW interrupts.
Also adapted TB to new addresses for debug registers.
Modified test cputest to try BREAK and SYSCALL opcodes.