Give ExecutionEngine of top level buffers.

Long term the idea if for the engine to not own the buffers, but for now
this is consistent with the rest of the API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216484 91177308-0d34-0410-b5e6-96231b3b80d8
Pass a MemoryBufferRef when we can avoid taking ownership.

The attached patch simplifies a few interfaces that don't need to take
ownership of a buffer.

For example, both parseAssembly and parseBitcodeFile will parse the
entire buffer before returning. There is no need to take ownership.

Using a MemoryBufferRef makes it obvious in the type signature that
there is no ownership transfer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216488 91177308-0d34-0410-b5e6-96231b3b80d8
Pass a std::unique_ptr<MemoryBuffer>& to getLazyBitcodeModule.

By taking a reference we can do the ownership transfer in one place instead of
expecting every caller to do it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216492 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a couple of debug info test cases to match the metadata schema change in r216239

Found these while testing something else.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216505 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Fold Sign-/Zero-Extend into the shift immediate instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216510 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Fix address simplification.

When a shift with extension or an add with shift and extension cannot be folded
into the memory operation, then the address calculation has to be materialized
separately. While doing so the code forgot to consider a possible sign-/zero-
extension. This fix folds now also the sign-/zero-extension into the add or
shift instruction which is used to materialize the address.

This fixes rdar://problem/18141718.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216511 91177308-0d34-0410-b5e6-96231b3b80d8
Remove type unit skeletons. GDB no longer needs them & this saves a heap of space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216521 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: Optimize GEP's involving ptrtoint better

We supported transforming:
(gep i8* X, -(ptrtoint Y))

to:
(inttoptr (sub (ptrtoint X), (ptrtoint Y)))

However, this only fired if 'X' had type i8*.  Generalize this to
support various types of different sizes.  This results in much better
CodeGen, especially for pointers to packed structs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216523 91177308-0d34-0410-b5e6-96231b3b80d8
Fix some cases were ArrayRefs were being passed by reference. Also remove 'const' from some other ArrayRef uses since its implicitly const already.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216524 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify creation of a bunch of ArrayRefs by using None, makeArrayRef or just letting them be implicitly created.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216525 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: Added intrinsic for VMOVSS store form with mask.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216530 91177308-0d34-0410-b5e6-96231b3b80d8
[SKX] Added new versions of cmp instructions in avx512_icmp_cc multiclass, added VL multiclass.
Added encoding tests


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216532 91177308-0d34-0410-b5e6-96231b3b80d8
Clang-format over X86AsmInstrumentation.*.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216536 91177308-0d34-0410-b5e6-96231b3b80d8
[SDAG] Re-instate r215611 with a fix to a pesky X86 DAG combine.

This combine is essentially combining target-specific nodes back into target
independent nodes that it "knows" will be combined yet again by a target
independent DAG combine into a different set of target-independent nodes that
are legal (not custom though!) and thus "ok". This seems... deeply flawed. The
crux of the problem is that we don't combine un-legalized shuffles that are
introduced by legalizing other operations, and thus we don't see a very
profitable combine opportunity. So the backend just forces the input to that
combine to re-appear.

However, for this to work, the conditions detected to re-form the unlegalized
nodes must be *exactly* right. Previously, failing this would have caused poor
code (if you're lucky) or a crasher when we failed to select instructions.
After r215611 we would fall back into the legalizer. In some cases, this just
"fixed" the crasher by produces bad code. But in the test case added it caused
the legalizer and the dag combiner to iterate forever.

The fix is to make the alignment checking in the x86 side of things match the
alignment checking in the generic DAG combine exactly. This isn't really a
satisfying or principled fix, but it at least make the code work as intended.
It also highlights that it would be nice to detect the availability of under
aligned loads for a given type rather than bailing on this optimization. I've
left a FIXME to document this.

Original commit message for r215611 which covers the rest of the chang:
  [SDAG] Fix a case where we would iteratively legalize a node during
  combining by replacing it with something else but not re-process the
  node afterward to remove it.

  In a truly remarkable stroke of bad luck, this would (in the test case
  attached) end up getting some other node combined into it without ever
  getting re-processed. By adding it back on to the worklist, in addition
  to deleting the dead nodes more quickly we also ensure that if it
  *stops* being dead for any reason it makes it back through the
  legalizer. Without this, the test case will end up failing during
  instruction selection due to an and node with a type we don't have an
  instruction pattern for.

It took many million runs of the shuffle fuzz tester to find this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216537 91177308-0d34-0410-b5e6-96231b3b80d8
[x86] Fix a regression introduced with r213897 for 32-bit targets where
we stopped efficiently lowering sextload using the SSE41 instructions
for that operation.

This is a consequence of a bad predicate I used thinking of the memory
access needs. The code actually handles the cases where the predicate
doesn't apply, and handles them much better. =] Simple fix and a test
case added. Fixes PR20767.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216538 91177308-0d34-0410-b5e6-96231b3b80d8
Add an explicit cast to pacify implicit boolean conversion warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216539 91177308-0d34-0410-b5e6-96231b3b80d8
Clang-format over X86AsmInstrumentation.* with LLVM style.

r216536 mistakenly used -style=Google instead of LLVM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216543 91177308-0d34-0410-b5e6-96231b3b80d8
[SLP] Re-enable vectorization of GEP expressions (re-apply r210342 with a fix).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216549 91177308-0d34-0410-b5e6-96231b3b80d8
Teach the AArch64 backend about v4f16 and v8f16

This teaches the AArch64 backend to deal with the operations required
to deal with the operations on v4f16 and v8f16 which are exposed by
NEON intrinsics, plus the add, sub, mul and div operations.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216555 91177308-0d34-0410-b5e6-96231b3b80d8
Limit the symbol search in DynamicLibrary to the module that was opened.

Differential Revision: http://reviews.llvm.org/D5030

Reviewed By: Reid Kleckner, Rafael Espindola

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216563 91177308-0d34-0410-b5e6-96231b3b80d8