Git Test
Version w/ LEON3 and 4-stage filter/decimator module
Added SPI core in VHDL and handling in C, and used firmware for testing (sw_buff_test.c).
7Seg and Test Module GPIO blocks added, initial test code for 7 Seg as well
7Seg finalizing and IP code modification
sevenseg.h and .c files added (display driver)
timer HW and SW code added, all slaves on APB restructured, defines for Nexys4 board GPIO resources added
Merged SoftwareBuffer into develop