Wasn't indexing into branch table correctly when loading them.

Removed filler NOPs
Corrected PC pipelining

Moved Controller output to stage 7, unregistered, else extra 0 PC messes sync across TIDs
Forgot a pipeline stage for PC in Branch_Check.
Hopefully the PC->I_mem crit path won't show up, since the Controller
is no longer depended on A, so can be placed/retimed better.
Commented out TID internal delay.

We don't need a write_thread address, since there are no internal writes
and the branch tables are fully mapped into H memory.

However: needs address translation at the write port, same for Addressing module in pattern_match branch.
Else we write to the wrong table entry due to offset memory mapping.