sunxi: dram: Tweak DEFE port setup to fix A10 screen shaking issue

When driving a 1920x1080-32@60Hz monitor, framebuffer scanout for
screen refresh becomes more bandwidth intensive and challening.
There used to be an old problem, which manifested itself as a
screen shaking effect when CPU or GPU are doing something memory
intensive and competing for the memory bandwidth with the display
controller. A possible explanation for it is that the display
controller just sends the previous scanline over HDMI in the case
if it can't read the current one in time.

Framebuffer scanout can be done either by DEBE or by DEFE. It seems
like DEBE is broken beyond repair. Apparently it is doing isolated
32 byte burst reads at regular intervals to scan out the framebuffer
and send this data over HDMI. The size of this burst is too small.
And if something else (CPU or GPU) is accessing memory at the same
time, we easily get bank conflicts with huge penalties. As these
penalties happen per 32 bytes of data, most of the memory bandwidth
is wasted. The end result is the screen shaking effect and a
significant performance loss for the CPU/GPU. This all is happening
because DEBE is configured to have higher priority than CPU and GPU.
So it can do these tiny bursts and nobody can do anything about it.
If we reduce the priority of DEBE, then the screen shaking effect
becomes much worse.

DEFE is somewhat similar to DEBE. But the key difference is that
it seems to implement some buffering of data and this buffer does
not underrun so easily. So it is possible to drop the priority
of DEFE port and make it the same as CPU/GPU. However in order to
get really perfect results, we need to also increase the "host port
command number" parameter. It is currently set to 0x10 by default
(the same as for CPU and GPU) and from what it looks, it affects
the bandwidth distribution between the ports with equal priority.
To experiment with this, I took A10-OLinuXino-LIME board (which
has a slow 16-bit memory interface) and downclocked DRAM to 408MHz.
Then used lima-memtester and glmark2-es2 programs to reproduce the
screen shaking effect. Increasing the "host port command number"
parameter resulted in a gradual reduction of the image glitches.
And at 0x50, the shaking effect disappeared completely.

So all that we need to do is a simple change "0x1035 -> 0x5031"
for the DEFE host port setup. And even A10-OLinuXino-LIME becomes
able to drive a FullHD monitor at 60Hz and 32bpp without issues
if "fb0_scaler_mode_enable" is set to 1 in the fex file.

Additionally, for A10-OLinuXino-LIME with DRAM clocked at 480MHz
and driving a 1920x1080-32@60Hz monitor in "scaler" mode, the
memset performance improves from 559.3 MB/s to 807.3 MB/s and
the memcpy performance improves from 299.3 MB/s to 317.9 MB/s
after this patch. So the memory bandwidth drain becomes smaller
the the overall system performance improves.

This has been also discussed at:
https://www.mail-archive.com/linux-sunxi@googlegroups.com/msg04085.html

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: fix SRAM_B/SRAM_D memory map

Move the B and D SRAM bank to their actual location (or at least
where the documentation pretends they are).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: hz parameter to clock_set_pll1 should be an unsigned int.

Requested by Marek during upstream review.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: add comments to pll1_para array.

The entries must be ordered by frequency and the final entry is a catchall
which configures the maximum supported frequency.

Make pll1_para static at the same time.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: HYP/non-sec: move switch to non-sec to the last boot phase

Having the switch to non-secure in the "prep" phase is causing
all kind of troubles, as that stage can be called multiple times.

Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: non-sec: reset CNTVOFF to zero

Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: add missing HYP mode constant

In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.

Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: add separate section for secure code

In anticipation of refactoring the HYP/non-secure code to run
from secure RAM, add a new linker section that will contain that
code.

Nothing is using it just yet.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: allow relocation to secure RAM

The current non-sec switching code suffers from one major issue:
it cannot run in secure RAM, as a large part of u-boot still needs
to be run while we're switched to non-secure.

This patch reworks the whole HYP/non-secure strategy by:
- making sure the secure code is the *last* thing u-boot executes
  before entering the payload
- performing an exception return from secure mode directly into
  the payload
- allowing the code to be dynamically relocated to secure RAM
  before switching to non-secure.

This involves quite a bit of horrible code, specially as u-boot
relocation is quite primitive.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: add generic ARMv7 PSCI code

Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: add the option for a second-stage monitor

Allow the switch to a second stage secure monitor just before
switching to non-secure.

This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: convert arch_fixup_memory_node to a generic FDT fixup function

Some architecture needs extra device tree setup. Instead of adding
yet another hook, convert arch_fixup_memory_node to be a generic
FDT fixup function.

[maz: collapsed 3 patches into one, rewrote commit message]

Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec/PSCI: emit DT nodes

Generate the PSCI node in the device tree.

Also add a reserve section for the "secure" code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
sunxi: HYP/non-sec: add sun7i PSCI backend

So far, only supporting the CPU_ON method.
Other functions can be added later.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
sunxi: HYP/non-sec: configure CNTFRQ on all CPUs

CNTFRQ needs to be properly configured on all CPUs. Otherwise,
virtual machines hoping to find valuable information on secondary
CPUs will be disapointed...

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>