Phy address detection

Due to different microSOM implementations the Atheros phy might appear
in two different addresses; 0x0 or 0x4 (depending on the reset strap
of the LED_ACT ping of the phy).
The microSOM that was with the carrier-one had a pull-down that forced
phy address to 0x0, where the microSOM with the CuBox-i (and future
HummingBoard) doesn't pull down and sometimes it's reset strap is
sampled as '0' and sometimes as '1' thus making the PHY address
either 0x0 or 0x4.

Since u-boot doesn't scan the mii bus this fix registers the phy first
on address 0x0, and upon failure it registers it on address 0x4.

With this patch a minor fix for the ENET_REF_CLK pad is introduced.
The pad doesn't need to pull/keep since it's driven by the phy at
125MHz (the phy's generated clock)

Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>