pic: make NMIs configurable

That the bottom two irqs are NMIs is something that comes from
the or1200 implementation, there is nowhere stated in the arch
spec about them.
This makes the number of NMIs configurable, to allow backwards
compatibility with or1200, but at the same time, the default
is changed to disable them.
alu: add alternative non-stall "PIPELINED" mul impementation

The "PIPELINED" mul implementation is similar to the
"THREESTAGE" implementation, but with the difference that
instead of stalling the pipeline while the multiply is performed
in execute stage, the pipelining of the multiply go 'along' with
the cpu pipeline.
I.e. the multiply operation will be finished in write-back stage,
and the result muxed directly into the register-file.

This comes with the following implications:
The two following instructions after the multiply
instruction can't have their input forwarded from
execute stage nor ctrl/mem stage. Instead, nop-bubbles
are inserted on such occations.

Since the result is not ready in execute stage,
generating multiply overflows becomes cumbersome and
has therefore been omitted.

While this gives a significant boost in multiply operations,
a multiply now takes (best case) 1 cycle instead of 3
(and coremark score sees about a 4% boost),
timing reports show worse timing score with this implementation.
However the worst critical paths looks unrelated to the
multiplier, so some further work here is needed.

On the other hand, comparing resource usage between the
"PIPELINED" and "THREESTAGE" implementations,
the "PIPELINED" takes less resources.
decode: do not generate illegal insn exception on l.msync

l.msync is a class II instruction, which means that it is
optional to implement.
However, this doesn't mean that the instruction should
generate an illegal instruction exception when it's not
implemented, instead the arch spec states that it should
instead be implemented as a no-op on implementations
that has strongly ordered memory accesses.

To be consistent, parameters are added for all three
sync instructions, l.msync, l.psync and l.csync.
None of them have actual implementations, and l.psync and
l.csync will generate illegal insn exceptions when their
parameters are defined as "NONE".
Merge branch 'master' of github.com:openrisc/mor1kx into multicore

Conflicts:
	rtl/verilog/mor1kx_cpu_espresso.v
	rtl/verilog/mor1kx_cpu_prontoespresso.v
	rtl/verilog/mor1kx_decode_execute_cappuccino.v