Enable the board/slot case where a subdevice is shared by one device in the config and another in the container.  Its all about things being optional and perhaps unconnected.

components/bias_16.hdl/bias_16.xml: make it iqstream both input and output
hdl/assemblies/patternbias/Makefile: add the split case with tx in the config, and rx in the container
hdl/assemblies/patternbias/lime_split_cont.xml: ditto
hdl/platforms/zed/zed.ucf: make the clock signal match more cases
hdl/primitives/platform/platform_pkg.vhd: define a default tieoff value for rawprops_in
-- support subdevices with unused raw prop inputs
tools/ocpigen/include/hdl-config.h: extra bookkeepping to record which indices are connected
-- for each device worker instance port
-- refactor subdevice connectivity to shared between config and container
tools/ocpigen/include/port.h: refactor devsignal port assignments to do tieoffs etc.
tools/ocpigen/include/wip.h: specialize cloning (externalizing) raw and devsignal ports.
tools/ocpigen/src/dev.cxx: ditto
tools/ocpigen/src/hdl-assembly.cxx: change naming convention for internal signals (use _i)
-- and refactor handling of internal connection signals
tools/ocpigen/src/hdl-config.cxx: enable finding subdevices in the config from the container
tools/ocpigen/src/hdl-container.cxx: ditto
tools/ocpigen/src/parse.cxx: prepare for more builtin parameter properties
tools/ocpigen/src/port.cxx: deal with unconnected ports, and cloning rawprop/devsignal ports