RTL: Remove wb_cas_unit from processor module

The processor core now has load-linked/store-conditional (l.lwa and
l.swa), so the workaround can be retired now.
RTL: Dualcore compute tile

With the new libc we can now run dual core tiles. Disable the data
cache for the moment.
RTL: Fix mor1kx traceport for rfe

The return from exception instruction does not advance after execute
stage, so we need to detect it and properly set the traceport.