exynos-drm: disable modes with too much blanking

The Exynos4412 display controller designer chose not to consult
the EDID spec when defining field bit-widths. As a result
the blanking parameters are only 8 bits in size.

Exclude modes which require more blanking than that, such as
1080p@50Hz.
Add more VPLL pixel clock frequencies

25.2MHz:
For 640x480@60Hz. We already have 25.175MHz for the Standard
Timing (DMT), but the Established Timing (originating from IBM/VGA)
requires 25.2MHz.

78.8MHz:
For 1024x768@75Hz. According to the EDID spec that should come from
VESA/DMT, for which we already have 78.175MHz. But a likely bug or
quirk in edid_est_modes[] means that Linux uses 78.8MHz here.
Merge pull request #9 from endlessm/shell/3714

Disable modes with too much blanking