ARM: dts: sun7i: Add uart3/4/5, i2c3 and spi2 pinmux

This patch add generic dts node for uart3/4/5, i2c3 and spi2.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: dts: sun7i: Add Merrii A20 Hummingbird board

This adds support for the A20 Hummingbird:
http://www.merrii.com/en/pla_d.asp?id=171

This patch enable most on-board peripherals supported on current kernel,
such as uart, i2c, spi, pwm, ohci/ehci, gmac and mmc.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun7i: Add support for Olimex A20-OLinuXino-LIME

This patch adds support for Olimex A20-OLinuXino-LIME board.

Signed-off-by: FUKAUMI Naoki <naobsd@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun6i: Relicense the A31 DTSI under GPLv2/X11

The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
ARM: sun7i: Relicense the A20 DTSI under GPLv2/X11

The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Alexander Bersenev <bay@hackerdom.ru>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Oliver Schinagl <oliver@schinagl.nl>
Acked-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
ARM: sun8i: Relicense the A23 DTSI under GPLv2/X11

The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Merge branch 'sunxi/dt-for-3.18' into sunxi/for-next
Merge branch 'sunxi/for-next' into sunxi-next
clk: sunxi: add correct divider table for sun4i-apb0 clock

The sun4i-apb0 clock, as found on all platforms using it, is a
power-of-two-based divider clock, with a special divider of 2
for value 0.

This was causing the clock framework to incorrectly calculate
the clock rate for apb1 and related modules on sun6i and sun8i.
On sun[4/5/7]i, u-boot SPL configures the divider with value 1
for /2 divider, so no suprises there.

This patch adds a proper divider table for it, so the correct
clock rate can be calculated.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Merge branch 'sunxi/clocks-for-3.18' into sunxi/for-next
ARM: dts: sunxi: Add fixed 5V regulator

Most if not all boards we've seen have a fixed 5V regulator, which is
the main power supply and/or fixed output of the PMIC.

Add this one to the common regulators DTSI.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: dts: sun5i: Add DT for HSG H702 tablet board

This is a Q8 format 7 inch tablet with an Allwinner A13 SoC.
It has 512MB DRAM, 4GB NAND flash, an accelerometer, camera,
RTL8188-based WiFi, and micro SD slot for external storage.

It is likely made by a subsidiary of Hanns.G (Hannstar).

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
rtc: sun6i: Add sun6i RTC driver

This patch introduces the driver for the RTC in the Allwinner A31 and
A23 SoCs.

Unlike the RTC found in A10/A20 SoCs, which was part of the timer, the
RTC in A31/A23 are a separate hardware block, which also contain a few
controls for the RTC block hardware (a regulator and RTC block GPIO pin
latches), while also having separate interrupts for the alarms.

The hardware is different enough to make a different driver for it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Varka Bhadram <varkabhadram@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtc

Now that we have Kconfig options for individual sunxi platforms, let
the rtc-sunxi driver depend on the platforms that actually have this
hardware, sun4i and sun7i.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: dts: sun8i: Add DMA controller node

Add the DMA controller node and DMA bindings to the supported devices.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Merge branches 'sunxi/dt-for-3.18' and 'sunxi/drivers-for-3.18' into sunxi/for-next
Merge branch 'sunxi/for-next' into sunxi-next
clk: sunxi: Add post clk divider for factor clocks

Some factor clocks, mostly PLLs, have an extra fixed divider just before
the clock output. Add an option to the factor clk driver config data to
specify this divider.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Fix PLL6 calculation on sun6i

The N factor for PLL6 counts from 1 to 32, as specified in the A23
manual, and shown in Allwinner's original A31 code.

Also the PLL6 factors alone calculate the clock rate for PLL6x2, not
the normal halved output for PLL6. This is what the factors clk
.recalc_rate callback expects.

This patch fixes the N factor in the clock driver, and adds a post
PLL divider of 2 to calculate the rate for PLL6.

A further patch (to the DT) should add a fixed-factor x2 clock as
the PLL6x2 output.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider

This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>