Use .data() instead of &x[0]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203516 91177308-0d34-0410-b5e6-96231b3b80d8
Move trivial getter into header.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203517 91177308-0d34-0410-b5e6-96231b3b80d8
Remove incomplete comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203518 91177308-0d34-0410-b5e6-96231b3b80d8
Fix undefined behavior in vector shift tests.

These were all shifting the same amount as the bitwidth.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203519 91177308-0d34-0410-b5e6-96231b3b80d8
Follow up to r203488. Code clean up to eliminate a lot of copy+paste.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203520 91177308-0d34-0410-b5e6-96231b3b80d8
MultiJITTest.cpp: Tweak getPointerToNamedFunction() to be aware of also Windows x64.

In import thunk, jmp is:
  - On x86, 0xFF 0x25 [disp32].
  - On x64, 0xFF 0x25 [pcrel32].

See also my r144178.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203523 91177308-0d34-0410-b5e6-96231b3b80d8
X86: Enable ISel of 16-bit MOVBE instructions.

When the MOVBE instructions are available, use them for 16-bit endian
swapping as well as for 32 and 64 bit.

The patterns were already present on the instructions, but weren't being
matched because the operation was unconditionally marked to 'Expand.'
Change that to be conditional on whether the MOVBE instructions are
available. Use 'rolw' to implement the in-register version (32 and 64
bit have the dedicated 'bswap' instruction for that).

Patch by Louis Gerbarg <lgg@apple.com>.

rdar://15479984

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203524 91177308-0d34-0410-b5e6-96231b3b80d8
Add helpers for getting scalar sizes of vector value types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203526 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Calculate store mask instead of using switch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203527 91177308-0d34-0410-b5e6-96231b3b80d8
Cleanup whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203529 91177308-0d34-0410-b5e6-96231b3b80d8
Object: rename ARMV7 to ARMNT

The official specifications state the name to be ARMNT (as per the Microsoft
Portable Executable and Common Object Format Specification v8.3).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203530 91177308-0d34-0410-b5e6-96231b3b80d8
Fix fixme: remove unused method.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203552 91177308-0d34-0410-b5e6-96231b3b80d8
GVN: merge overflow intrinsics with non-overflow instructions.

When an overflow intrinsic is followed by a non-overflow instruction,
replace the latter with an extract. For example:

  %sadd = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
  %sadd3 = add i32 %a, %b

Here the add statement will be replaced by an extract.

When an overflow intrinsic follows a non-overflow instruction, a clone
of the intrinsic is inserted before the normal instruction, which makes
it the same as the previous case. Subsequent runs of GVN can then clean
up the duplicate instructions and insert the extract.

This fixes PR8817.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203553 91177308-0d34-0410-b5e6-96231b3b80d8
GVN: fix hashing of extractvalue.

My last commit did not add the indexes to the hashed value for
extractvalue. Adding that back in.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203558 91177308-0d34-0410-b5e6-96231b3b80d8
IR: add a second ordering operand to cmpxhg for failure

The syntax for "cmpxchg" should now look something like:

	cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic

where the second ordering argument gives the required semantics in the case
that no exchange takes place. It should be no stronger than the first ordering
constraint and cannot be either "release" or "acq_rel" (since no store will
have taken place).

rdar://problem/15996804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203559 91177308-0d34-0410-b5e6-96231b3b80d8
Remove copy ctors that did the same thing as the default one.

The code added nothing but potentially disabled move semantics and made
types non-trivially copyable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203563 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: simplify EmitAtomicBinary64

ATOMIC_STORE operations always get here as a lowered ATOMIC_SWAP, so there's no
need for any code to handle them specially.

There should be no functionality change so no tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203567 91177308-0d34-0410-b5e6-96231b3b80d8
[lit] Fix non-function style print statement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203573 91177308-0d34-0410-b5e6-96231b3b80d8
Fix crash in PRE.

After r203553 overflow intrinsics and their non-intrinsic (normal)
instruction get hashed to the same value. This patch prevents PRE from
moving an instruction into a predecessor block, and trying to add a phi
node that gets two different types (the intrinsic result and the
non-intrinsic result), resulting in a failing assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203574 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: enable tail call optimisation on Thumb 2

Tail call optimisation was previously disabled on all targets other than
iOS5.0+.  This enables the tail call optimisation on all Thumb 2 capable
platforms.

The test adjustments are to remove the IR hint "tail" to function invocation.
The tests were designed assuming that tail call optimisations would not kick in
which no longer holds true.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203575 91177308-0d34-0410-b5e6-96231b3b80d8