hdl/ip_cores/dsp-cores: update submodule reference
hdl/modules/pcie/*/Manifest.py: removed unexisting module

 - Removed unexisting module from Manifest files.
 	It was referenced here by error.
hdl/testbench/*/wb_acq_core_test/*: add instructions on README

There is an error when simulating the RS232 module with
modelsim. For now, it is safe to exclude the file from the
Manifest file (see README), as we do not use it in simulation.
hdl/top/ml605/*/*fmc130m_4ch_pcie.vhd: add debug signals

Also, some unnecessary comments were removed
hdl/syn/ml605/*_fmc130m_4ch_pcie/*: update syn files
Merge branch 'pcie-test' into dsp-devel
hdl/platform/virtex6/chipscope/*: add new ILA components

Add ILA with 5 32-bit ports and buffer size of
1024 and 8192
hdl/top/ml_605/*_dsp_fmc130m_4ch/*: update Top module

Add debug signals the Windowing algorithm
hdl/syn/ml605/*_dsp_fmc130m_4ch/*: update syn files
hdl/ip_cores/dsp-cores: update submodule reference