* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.


git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@27934 3ad0048d-3df7-0310-abae-a5850022a9f2
m68k: try to generate a bit smaller code in g_adjust_self; also changed two JMPs to S_NO from S_L, because JMP is unsized anyway

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@27935 3ad0048d-3df7-0310-abae-a5850022a9f2