Convert register file to Altera dual-port RAM

- remove test output from register file
- add .bak files to .gitignore
Fleshing out initial design

* added pll for register file (runs at 2x system clock)
* need to clean up single and dual port RAMs (not simulating anyways)
* broke out opcode, register and some instruction fields into defines.sv
* added test for vcpu (currently named tbemicro_sdk.v, need to fix)
* added instruction fetch (vcpu_if.v), instruction decode (vcpu_id.v),
  and instruction execute (vcpu_ex.v) stages to the pipeline
* added a couple of opcodes for simple tests and defined some instruction
  formats
* branching and read-after-write work in limited testing