be: change pre spill prepare phase to work on all register classes at once

- Only iterating over the graph once should be slightly faster
- We don't need to insert the middle of register allocation logic but
  can perform it once before.
- We can gather statistics on the prepared graph before spilling/regalloc has
  happened.
amd64: dump IMM64 attributes in graph
new copy/value statistics
fix warning
amd64: abort when spilling float values (instead of producing invalid code)
statev: cleanup, optimized hot function, show warnings if something fails
remove overly verbose statevs for now
bera: improve statistics for add_missing_copies()
bespillutil: cleanup, use C99
bespillutil: use irnodehashmap+linked lists instead of set and ARR_F

- the linked lists are introduced to get a deterministic order
- irnodehashmap instead of set should be slightly faster
coding style fixes: ensure space after control flow changing statements