clk: add helper for unique DT clock names

Currently, most DT clock drivers pick a unique node name to allow unique
clock names. As ePAPR recommends node names to be generic, we therefore
provide a helper to generate a unique clock name from the DT node name
plus reg property or a magic number instead. This is basically the same
we already do for proper devices and may vanish as soon as there is some
(early) device support for clocks available.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
clk: berlin: add driver for BG2x audio/video PLL

This is a driver for the dual-VCO PLL with 8 channels each found on
Marvell Berlin2 SoCs. While both VCOs share the same register set,
sometimes registers shifts for one of the VCOs is a bit off. Nothing
serious that should require a separate driver, so deal with both VCOs
in a single driver instead.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
clk: berlin: add driver for BG2x simple PLLs

This is a clock driver for the simple PLLs found on Berlin SoCs.
With repect to PLL registers and features, BG2/BG2CD and BG2Q are
slightly different, e.g. different allowed VCO dividers and bit
shifts.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
clk: berlin: add driver for BG2x complex divider cells

This is a driver for the complex divider cells found on Marvell Berlin2
SoCs. The cells come in two flavors: single register cells and shared
register cells. The single register cells are registered by using a DT
node, while the shared ones will be taken care of in a SoC-specific
core clock driver.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
clk: berlin: add core clock driver for BG2/BG2CD

This driver deals with the core clocks found on Marvell Berlin
BG2 and BG2CD. For the shared register dividers, make use of the
corresponding driver and add some single clock muxes and gates for
the rest.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Merge branch 'topic/clk-driver' into berlin/for-next