sim: cpu_sim: correct branches, predicates on other_instrs, and parallel lanes

Correct multiple issues:
- Branch target computation was incorrectly handling:
  - branches to registers
  - offset values (were not being scaled by 16x as specced)
  - negative offset values (were not being correctly sign extended)
- Instructions in a packet were not being executed in parallel.
- 'Other' instructions were not correctly obeying predicates.