[ARM] arm64: Trap data cache operation by set/way

On SMP host, just upgrading data cache set/way
operations to clean+invalidate operations won't
suffice.

If a VCPU is preempted while it was doing
clean/invalidate/clean+invalidate by set/way
on host CPU A and resumed on host CPU B then
effects of set/way operations will not be
correctly seen by all host CPUs. To take care
of this clean/clean+invalidate entire data cache
by set/way when such a VCPU is resumed on another
host CPU.

This approach is very similar to what we already
for set/way operations on arm32ve port.

Signed-off-by: Anup Patel <anup@brainfault.org>