target-ppc: Add POWER8's FSCR SPR

This adds an FSCR (Facility Status and Control Register) SPR. This defines
names for FSCR bits.

This defines new exception type - POWERPC_EXCP_FU - "facility unavailable" (FU).
This registers an interrupt vector for it at 0xF60 as PowerISA defines.

This adds spr_write_and_tb_flush() and TCG's helper_tb_flush() to reset
translation blocks on FSCR write.

This adds a TCG helper_fscr_facility_check() helper to raise an exception
if the facility is not enabled. It also updates the interrupt cause field
in FSCR. This adds a TCG translation block generation code. The helper
may be used for HFSCR too as it has the same format.

The helper raising FU exceptions is not used by this patch but will be
in the next ones.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
target-ppc: Enable FSCR facility check for TAR

This makes user-privileged read/write fail if TAR facility is not enabled
in FSCR.

Since this is the very first check for enabled in FSCR facility,
this also adds gen_fscr_facility_check() for using in spr_write_tar()/
spr_read_tar().

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
target-ppc: Add POWER8's MMCR2/MMCRS SPRs

This adds POWER8 specific PMU MMCR2/MMCRS SPRs.

This adds a spr_write_ureg helper for changing a hypv-privileged SPR when
it is accessed via its user-privileged mirror. A spr_read_ureg() is
already there. Since the new helper is only used by book3s CPUs, it is
limited to TARGET_PPC64 to make gcc happy when QEMU is compiled for 32 bit.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
target-ppc: Add POWER8's TM SPRs

This adds TM (Transactional Memory) SPRs.

This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
Since this is not the only register like that and their numbers go
consequently, it makes sense to generalize the helpers.

This adds a gen_msr_facility_check() helper which purpose is to generate
the Facility Unavailable exception if the facility is disabled.
It is a copy of gen_fscr_facility_check() but it checks for enabled
facility in MSR rather than FSCR/HFSCR. It still sets the interrupt cause
in FSCR/HFSCR (whichever is passed to the helper).

This adds spr_read_tm/spr_write_tm/spr_read_tm_upper32/spr_write_tm_upper32
which are used for TM SPRs.

This adds TM-relates MSR bits definitions.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
KVM: target-ppc: Enable transactional state migration

This adds migration support for registers saved before transaction started.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs

POWER8 supports Event-Based Branch Facility (EBB). It is controlled via
set of SPRs access to which should generate an "Facility Unavailable"
interrupt if the facilities are not enabled in FSCR for problem state.

This adds EBB SPRs.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
target-ppc: Enable PPR and VRSAVE SPRs migration

This hooks SPR with theit "KVM set_one_reg" counterparts which enables
their migration.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
spapr_hcall: Split h_set_mode()

This moves H_SET_MODE_RESOURCE_LE handler to a separate function
as there are other "resources" coming and this is going to become ugly.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
v2:
* s/becode/become/ in commit log
spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE

This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
the H_SET_MODE, for POWER8 (PowerISA 2.07) only.

This defines AIL flags for LPCR special register.

This changes @excp_prefix according to the mode, takes effect in TCG.

This turns support of a new capability PPC2_ISA207S flag for TCG.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
spapr: Enable DABRX special register (new SPR)

This advertises Data Address Breakpoint Register Extension (DABRX) to
the guest via hyperrtas list and enables it to migrate.

This implements H_SET_XDABR.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>