mor1kx-generic: add debug tap and jtag server support

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
atlys/clkgen: remove defparams
atlys: remove invalid DIVIDE(2) on BUFIO

Newer ISE (reported on >= 14.5) fail to build designs with
BUFIO2 that has the DIVIDE parameter set to 2.
The error message is:
"ERROR:PhysDesignRules:2502 - Issue with pin connections and/or
configuration on
   block:<dvi_gen0/sysclk_div>:<BUFIO2_BUFIO2>.  BUFIO2 has an invalid
setting
   of DIVIDE by 2. This setting is not supported. For more information
please
   see Answer Record 56113.
ERROR:Pack:1642 - Errors in physical DRC."

And, Answer Record 56113 states the following:
"In Spartan-6 FPGA, the BUFIO2 using the DIVIDE(2) applications can
occasionally enter a stuck state. Hence, it is not supported and an
alternative implementation needs to be used."

To get around this, instead of feeding the 100 MHz system clock
into dvi_gen, an already divided by 2 50MHz clock is used.
atlys: add timing constraints for dvi_gen CDC
wb_altera_ddr_wrapper: fix read_done CDC problems

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
wb_altera_ddr_wrapper: fix classic wb transaction

In some circumstances there might be an unwanted wb_ack while
doing classic wishbone access.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
verilator_tb_utils: VerilatorTbUtils::doJTAG: check if jtag is enabled
mor1kx-generic: tb.cpp: check for NOP_EXIT_SILENT
cores: add cfi_ctrl from opencores

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
wb_port_arbiter: fix cache coherency during wb block write

Multiples write can occur during a single write block cycle.

Old code triggers a buffer write on the rising edge of wb_cyc.
This only works with single write cycles.

This patch signals that a write have happend to all ports
on every wb_ack during the write block cycle.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
systems: add Altera NEEK board

This patch adds supports for the Altera NEEK board.

The systems supports:
- UART,
- Ethernet,
- VGA/LCD controller,
- SD-CARD (SPI mode),
- NOR flash.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
verilator_tb_utils: close vcd dump in destructor
misc WIP
de0_nano: connect debug rst to mor1kx
wb_intercon: fix slaves data port size

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
de1: remove wb_data_resize from orpsoc_top.v

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
adv_debug_sys: fix 32 bits wb access in jsp module

Old code depends on address bits [1:0] to be update during
a 8 bits access on a 32 bits bus. The OR1200 does that.

Because it is not in the wishbone specification, we can't rely
on this. For example, mor1kx set address bits [1:0] to "00".

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
mt48lc16m16a2: Add convenience wrapper for test benches

This adds a wrapper that takes care of preloading RAM from ELF files
and adds simulated delay on the data lines.
mt48lc16m16a2: Add wrapper file to .core
mt48lc16m16a2: Fix problems that were introduces with the wrapper

This patch adds simulation dependencies on wiredelay and elf-loader.
It also removes an `include statement for a non-existing file