Remove temporary front end scaffolding for Cat{Even,Odd}Lanes
and Interleave{LO,HI} operations, and instead generate real
UZP1/UZP2/ZIP1/ZIP2 instructions in the back end. 



git-svn-id: svn://svn.valgrind.org/vex/trunk@2876 8f6e269a-dfd6-0310-a8e1-e2731360e62c
arm64: implement: abs d_d, neg d_d, abs std7_std7, addhn, subhn, raddhn, rsubhn


git-svn-id: svn://svn.valgrind.org/vex/trunk@2877 8f6e269a-dfd6-0310-a8e1-e2731360e62c