msm: clock-local: Check for NULL branch ctl_reg

Branch clocks will soon be used for reset-only purposes, in which
case the ctl_reg field will be NULL. Update the handoff and
clk_disable code to check for a NULL register address before
reading the register.

Change-Id: I0a674409d6742cb2b03f972465bc80d15afc8664
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: clock-8960: Move DSI resets functionality to their own clocks

The DSI core resets are currently associated with the DSI byte clocks
because the DSI core clocks are managed by the DSI driver directly,
not the clock driver. Move the reset functionality out of the byte
and into their own reset-only branch clocks so that the footswitch
driver, which needs to assert these resets, can do so without
involving the unrelated byte clock.

Change-Id: I65a84e97181c5461c5f2e0b0af19dc6b0b1d2557
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: footswitch-8x60: Reset DSI domain along with MDP collapse/restore

Some DSI-related logic lives in MDP's collapsible GDHS domain for
896 and 8064. Assert the reset to this domain when the reset of MDP
is reset. Use of the reset-only clocks added here assumes the
display driver is making sure the DSI clocks (not managed by the
clock driver) are enabled for the duration of the collapse and
restore sequences so that the resets propagate.

Change-Id: Ife1b13e22e35b322ff5da75280b3c8d9d5027743
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm_fb: Remove control of HDMI PLL regulator

The regulators required by the HDMI PLL are now controlled within
the clock driver. Remove the explicit control from mdp.c.

Change-Id: Ia2975a5a83b77cd9e21fc43cabea754b7b040dd5
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msm: display: Add DSI clock control for MDP GDHS power collapse

Enable DSI clock and regulator before enabling/disabling power collapse
for MDP GDHS.

Change-Id: I9effb5b4e9ca8033c51085260c8fb9f32c422dd3
Signed-off-by: Ravishangar Kalyanam <rkalya@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Merge "msm_fb: Remove control of HDMI PLL regulator"
Merge "msm: display: Add DSI clock control for MDP GDHS power collapse"
Merge "msm: clock-local: Check for NULL branch ctl_reg"
Merge "msm: clock-8960: Move DSI resets functionality to their own clocks"
Merge "msm: footswitch-8x60: Reset DSI domain along with MDP collapse/restore"
Perf: Change IRQ functions for CPU variants

Unicore targets can't use the percpu IRQ API,
so fallback to the generic versions of the functions
at init.

Change-Id: Ifdf16aa50d3f577ec2ea400c59578e5f2a5058c8
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
(cherry picked from commit 9f5f89411e3c750827e566f07c0e71500ed93fb7)
(cherry picked from commit d40c06b30e24f7b8ad9d7c6fb6f4293c38524509)

Signed-off-by: Gopal Goberu <ggober@codeaurora.org>
Merge "Perf: Change IRQ functions for CPU variants"
msm: kgsl: Faster GPU hang detection

Check global GPU status registers in intervals of 2 seconds,
if the registers did not change after 2 seconds trigger a hang.
When there is an actual GPU hang and GPU is stalled, this reduces
the current hang detection time from 10 seconds to 2 seconds.
Faster GPU hang detection reduces the overall time to recover
from GPU hang.

Change-Id: If432ccacc1b77b4fc7f08b756886bd3ae5edf04f
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>

Conflicts:

	drivers/gpu/msm/adreno.c
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>

Signed-off-by: Ramakrishna Prasad N <crpn@codeaurora.org>
msm: kgsl: Ensure glitch free changing of the GPU frequency

If there are requests to skip levels while the clocks are on
be sure to hit the intermediate frequencies.

Change-Id: Ib69bcbc7eb87532c090b4ede28d967e4cd0f08ec
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
Signed-off-by: Ramakrishna Prasad N <crpn@codeaurora.org>
msm: kgsl: Allow the wait_timeout to be disabled

With the improved hang detection we don't technically need a upper
timeout bound for a process to wait in waitfortimestamp().  Allow
for a idle_timestamp of '0' to allow the loop to wait for ever.
The infrastructure for changing the idle_timeout still exists
so it can be changed to whatever value is appropriate for debugging
or testing.

CRs-fixed: 382366
CRs-fixed: 383999
Change-Id: Ic0dedbadf2c100eb56ed2338914575061776e725
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Michael Street <mstreet@codeaurora.org>

Conflicts:

	drivers/gpu/msm/adreno.c
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>

Signed-off-by: Ramakrishna Prasad N <crpn@codeaurora.org>
msm: kgsl: Don't use 'wait_timeout' in the idle functions

There are two distinct parts of the code that may need to loop waiting
for the GPU to complete a task: waiting for a timestamp and waiting
for the entire core to go idle. Waiting for a timestamp technically
doesn't need a timeout since the only downside is a process that sleeps
forever with an interruptible timeout. Waiting for the core to go idle
is more problematic because it is a busy wait and it is the last point
we can safely detect a GPU hang.

Beacuse we can (and will) not use a timeout in wait for timestamp, we
need to institute a new timeout value to be used in idle. Nowhere the
idle function is called uses a custom value for the timeout, so remove
that parameter from the calls and use a static timeout value in the
core specific functions.

Change-Id: Ic0dedbad9ecd2044c34e4cec551dc7f53b253f3d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

Signed-off-by: Michael Street <mstreet@codeaurora.org>

Conflicts:

	drivers/gpu/msm/adreno.c
	drivers/gpu/msm/adreno_a3xx.c
	drivers/gpu/msm/kgsl_gpummu.c
	drivers/gpu/msm/kgsl_iommu.c
	drivers/gpu/msm/z180.c
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>

Signed-off-by: Ramakrishna Prasad N <crpn@codeaurora.org>
wcnss: Add interface to Reset wcnss

Add wcnss reset interface, this interface generates an FIQ to Riva.
Upon receiving this interrupt, Riva will execute the ERR_FATAL
routine and invoke SSR.

Change-Id: I74c293121cb69b312ed980902a12019adb700792
Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>

Conflicts:

	drivers/net/wireless/wcnss/wcnss_wlan.c

Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>
Merge "wcnss: Add interface to Reset wcnss"
Merge "msm: kgsl: Faster GPU hang detection"
Merge "msm: kgsl: Ensure glitch free changing of the GPU frequency"