CHERRY-PICK: CHROMIUM: video: tegra: fix a race in suspend sequence

There is a possible race condition between devfreq
and suspend sequence. To prevent race between scaling and gk20a
shutdown from happening, ensure devfreq is disabled before
shutting down gk20a.

BUG=chrome-os-partner:28174
TEST=System boots and LP0 stress passed 2900+ cycles

Original-Change-Id: I5c2fe02462f193494b05a50b0e566534ec6c9c07
Signed-off-by: Daehyoung Ko <dko@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/203700
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Mark Zhang <markz@nvidia.com>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
(cherry picked from commit 42c3db7d0086811df56107fdd9c53dc47f97e6fa)

Change-Id: I12a645f48fda519dd4eaad315ca5cb6e4509ec2a
Reviewed-on: https://chromium-review.googlesource.com/205748
Tested-by: Neil Chen <neilc@nvidia.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Commit-Queue: Neil Chen <neilc@nvidia.com>
CHERRY-PICK: CHROMIUM: video: tegra: Initialize FECS explicitly on recovery

Instead of calling second phase of PMU boot sequence, initialize FECS
directly.

BUG=chrome-os-partner:28174
TEST=System boots and LP0 stress passed 2900+ cycles

Original-Change-Id: I2cda45d663c177fea6e0fb8b1f787fe231c9ffb1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/203608
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Mark Zhang <markz@nvidia.com>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
(cherry picked from commit 8af7daae8ba6b670ab250a4abf79805748058942)

Change-Id: Ifa377118049eeb722e6e04de9f7a5a2e1d1c0d5c
Reviewed-on: https://chromium-review.googlesource.com/205757
Tested-by: Neil Chen <neilc@nvidia.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Commit-Queue: Neil Chen <neilc@nvidia.com>
CHERRY-PICK: CHROMIUM: video: tegra: Remove deferred ELPG enable

Prevent the disable ELPG routine from calling deferred re enablement of
ELPG. Remove code related to deferred ELPG enable.

BUG=chrome-os-partner:28174
TEST=System boots and LP0 stress passed 2900+ cycles

Original-Change-Id: I62be0a348a45d8fc9f2a28b99e2f30444251a36b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/203607
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
(cherry picked from commit 4c20996f3f2c89c411689dfadbdcc6029ccc84a8)

Change-Id: I44e129a120aeccd4a8f2ddd9af60422651606ac6
Reviewed-on: https://chromium-review.googlesource.com/205747
Tested-by: Neil Chen <neilc@nvidia.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Commit-Queue: Neil Chen <neilc@nvidia.com>
CHERRY-PICK: CHROMIUM: video: tegra: Add PMU sent/recvd messages to dbg log

Add debug log entries for received and sent PMU messages.

BUG=chrome-os-partner:28174
TEST=System boots and LP0 stress passed 2900+ cycles

Original-Change-Id: I180cdd1480813d71f36544fdd992e3002b62deb6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/203606
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
(cherry picked from commit 2aaaeed00d8b3ffe6411cb2040d7f073b6da065b)

Change-Id: I73171b80143a8f3371b15a3a05963917f47181a3
Reviewed-on: https://chromium-review.googlesource.com/205646
Tested-by: Neil Chen <neilc@nvidia.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Commit-Queue: Neil Chen <neilc@nvidia.com>
CHERRY-PICK: CHROMIUM: video: tegra: Do not clear PMU state on rail gate

When rail gating, we cleared all PMU status. Clear only the relevant
fields.

BUG=chrome-os-partner:28174
TEST=System boots and LP0 stress passed 2900+ cycles

Original-Change-Id: Ib9bd35f7cadd0d3f0572247eacc4939a53558c78
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/203605
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Mark Zhang <markz@nvidia.com>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
(cherry picked from commit 6ca5b9563f2c7d53fdb6f3d0e31dfe5e25e5663a)

Change-Id: I45889348783d5ea99b89372307fc8a38ebace374
Reviewed-on: https://chromium-review.googlesource.com/205756
Tested-by: Neil Chen <neilc@nvidia.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Commit-Queue: Neil Chen <neilc@nvidia.com>
CHERRY-PICK: CHROMIUM: video: tegra: Rewrite PMU boot-up sequence

Rewrite PMU boot sequence as a state machine. At PMU power-up send
initial messages, and reset state machine. At each reply from PMU,
do the next stage of PMU boot and set state.
As now PMU and FECS boot are independent, we need to ensure engine
idle before saving ZBC.
BUG=chrome-os-partner:28174
TEST=System boots and LP0 stress passed 2900+ cycles
Original-Change-Id: I3c308f2481d16628ea933dbd27ae91202a2c3d80
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/203609
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>

Change-Id: I330f801b5139fc4aa70ad1559a9617a3a11e8ae4
Reviewed-on: https://chromium-review.googlesource.com/205817
Tested-by: Neil Chen <neilc@nvidia.com>
Commit-Queue: Neil Chen <neilc@nvidia.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
CHROMIUM: clk: tegra124: initialize pll_d

There are chances in some chips that pll_d will fail to lock with
the hardware default m, n, and p value if the bootloader doesn't init
the pll first. Therefore we should init the pll instead of relying on
the bootloader.

BUG=chrome-os-partner:29836
TEST=Built kernel and boot. PLL_D can be enabled correctly.

Change-Id: I681b993dd0f3794048caed74143ebb9c0c6113bc
Signed-off-by: Danny Huang <dahuang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/205752
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205907
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Commit-Queue: Artiste Hsu <chhsu@nvidia.com>
Tested-by: Artiste Hsu <chhsu@nvidia.com>
CHROMIUM: ARM: dts: big: add EMC table with RAM code 6

Add Big EMC table with RAM code = 6.

BUG=chrome-os-partner:29501
TEST=Built kernel and boot

Change-Id: Id7ede742ac9366d204a3637a74f0312e097465ff
Signed-off-by: Danny Huang <dahuang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/203044
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/206645
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Commit-Queue: Star Lin <star_lin@compal.com>
Tested-by: Star Lin <star_lin@compal.com>
CHROMIUM: ARM: dts: big: update EMC table of RAM code 4

Update the Big EMC table with optimized value.

BUG=chrome-os-partner:29501
TEST=Built kernel and boot

Change-Id: I22f85432e1364b24d57808620e7ec22ba336619b
Signed-off-by: Danny Huang <dahuang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/203043
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/206629
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Commit-Queue: Star Lin <star_lin@compal.com>
Tested-by: Star Lin <star_lin@compal.com>
CHROMIUM: ARM: dts: blaze: Limit SD card to SDR50 mode

BUG=chrome-os-partner:30264
TEST=UHS-I SDHC SD card works fine on blaze and big.

Change-Id: I169155c15a552bbb976230ec1d3c5bef3e4b7284
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/206789
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
(cherry picked from commit f9b4e3cb0d31d6fd4407167b76ed8d74163449eb)
Reviewed-on: https://chromium-review.googlesource.com/207111
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
CHROMIUM: HACK: mmc: tegra: don't clock gate across suspend/resume

Sometimes the Marvell SD8897 generates a SDIO interrupt after it should
have been suspended, which will cause a hard hang if the SDIO IRQ thread
runs while the clock is gated.  Don't clock gate the SDHCI host to avoid
this hang.

Note that this only works around the hard hang issue.  If the SDIO IRQ
thread runs after the host has been suspended, there are likely to be
other issues, e.g. MMC transfers issued by the IRQ thread failing or
timing out.

BUG=chrome-os-partner:28553
TEST=10000 LP0 iterations pass

Change-Id: Icddc460332054503a26b495e7536468e4943847c
Signed-off-by: Peer Chen <pchen@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/206800
(cherry picked from commit bd35685295ff5e2845029b59b6132ae548417397)
Reviewed-on: https://chromium-review.googlesource.com/206975
Tested-by: Artiste Hsu <chhsu@nvidia.com>
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Commit-Queue: Artiste Hsu <chhsu@nvidia.com>