hdl/modules/wb_position_calc/wb_*: change CDC fifo size to 16
hdl/modules/*/wb_position_calc_core.vhd: don't use sys_clr for now

This was causin a shift in the TDM streams as not all blocks
implement sys_clr synchronization properly. See issue #15 in
https://github.com/lerwys/dsp-cores/issues