verify-di: Add back braces for MSVC compatability

Fixup after r206300.

<rdar://problem/15500563>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206305 91177308-0d34-0410-b5e6-96231b3b80d8
LTO: Add more loop simplification passes to LTO

Similar to r202051, add missing loop simplification passes to the LTO
optimization pipeline.

Patch by Rafael Espindola.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206306 91177308-0d34-0410-b5e6-96231b3b80d8
Split byval argument initialization so the memcpy(s) are injected at the
beginning of the first new block after inlining.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206307 91177308-0d34-0410-b5e6-96231b3b80d8
Add lifetime markers for allocas created to hold byval arguments, make them
appear in the InlineFunctionInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206308 91177308-0d34-0410-b5e6-96231b3b80d8
Use unique_ptr to manage ownership of child Regions within llvm::Region

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206310 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r191049/r191059 as it can produce wrong code (see PR17975).
It has already been reverted on the 3.4 branch in r196521.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206311 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM64] Set default CPU to generic instead of cyclone.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206313 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Improve the lowering of packed shifts by constant build_vector.

This patch teaches the backend how to efficiently lower logical and
arithmetic packed shifts on both SSE and AVX/AVX2 machines.

When possible, instead of scalarizing a vector shift, the backend should try
to expand the shift into a sequence of two packed shifts by immedate count
followed by a MOVSS/MOVSD.

Example
  (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))

Can be rewritten as:
  (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))

[with X and Y ConstantInt]

The advantage is that the two new shifts from the example would be lowered into
X86ISD::VSRLI nodes. This is always cheaper than scalarizing the vector into
four scalar shifts plus four pairs of vector insert/extract.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206316 91177308-0d34-0410-b5e6-96231b3b80d8
Make FastISel::SelectInstruction return before target specific fast-isel code
handles Intrinsic::trap if TargetOptions::TrapFuncName is set.

This fixes a bug in which the trap function was not taken into consideration
when a program was compiled without optimization (at -O0).

<rdar://problem/16291933>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206323 91177308-0d34-0410-b5e6-96231b3b80d8
[Allocator] Remove a really problematic overload. This is very confusing
because there is another (size_t, size_t) overload of Allocator, and the
only distinguishing factor is that one is a tempalte and the other
isn't. There was only one usage of this and that one was easily
converted to carry the alignment constraint in the type itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206325 91177308-0d34-0410-b5e6-96231b3b80d8
[Allocator] Fold the two templated overloads into a single one with
a default argument. The allocator interface we're modeling doesn't
distinguish between array and non-array allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206327 91177308-0d34-0410-b5e6-96231b3b80d8
RegionInfo: Do not access a value that was just moved away

This fixes a regression introduced in r206310.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206328 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Fix loads of i1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206330 91177308-0d34-0410-b5e6-96231b3b80d8
Make this test not match its own filename, when being run from a path that includes the string 'add'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206331 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Cleanup parsing of register names.

Try to figure out the class and number of subregisters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206334 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Print more immediates in hex format

Print in decimal for inline immediates, and hex otherwise. Use hex
always for offsets in addressing offsets.

This approximately matches what the shader compiler does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206335 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Print code size along with used registers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206336 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM64,C++11] Clean up the ARM64 LOH collection pass.

Range'ify a bunch of loops, mainly. As a result, we have a variety
of objects via reference rather than by pointer, so propogate that
through the various helper functions where it makes sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206337 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: Nuke some dead code.

Missed in previous commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206343 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM64,C++11] Tidy up branch relaxation a bit w/ c++11.

No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206344 91177308-0d34-0410-b5e6-96231b3b80d8