Fixed build with gcc 4.6
Fixed writing of $lut cells in BLIF backend
Merge branch 'master' of github.com:cliffordwolf/yosys
Fixed another bug in write_blif handling of $lut cells
Checking existence of ports in "hierarchy -check"
Added $dffe support to write_verilog
Added DFFE support to "abc" pass
Fixed "abc" pass for clk and enable signals driven by logic
Added support for multiple clock domains to "abc" pass
Added "abc -markgroups"
Added "show -colorattr"
Indenting fix in show.cc
Improved ABC clock domain partitioning
Renamed extend() to extend_xx(), changed most users to extend_u0()
Improvements in simplemap api, added $ne $nex $eq $eqx support
Added support for gate-level cells in dff2dffe
Added "dff2dffe -unmap"
Added "dff2dffe -direct" for direct gate mapping
Added "dfflibmap -prepare"
Added "dfflibmap -prepare" help