Experiment with tsc invariant detection.

Modern Intel and AMD processors have synchronized, constant rate timer support, which means no binding to CPU is necessary:

	17.12.1 Invariant TSC

	The time stamp counter in newer processors may support an enhancement, referred
	to as invariant TSC. Processors support for invariant TSC is indicated by CPUID.80000007H:EDX[8].
	The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. This is
	the architectural behavior moving forward. On processors with invariant TSC
	support, the OS may use the TSC for wall clock timer services (instead of ACPI or
	HPET timers). TSC reads are much more efficient and do not incur the overhead
	associated with a ring transition or access to a platform resource.

We can check for this during profliing and avoid binding to a CPU, which improves performance in synthetic benchmarks by up to 50%.