Added a simple TLB model for HybridSim's tags.
Moved tlb code into a separate function. Also prevent tlb from being checked for SYNC_ALL_COUNTER transaction, since this does not need the TLB.
Added comment for tlb stuff.
Merge branch 'master' into sync
Added counters for tlb miss and tlb hit
Added the ability to bypass TLB code by setting TLB_SIZE=0.
Updated extract to include the try-except block if the hybridsim.log
file exists but the yml file is empty.
Minor fix to extract.py
Switched extract.py to use mstats for collecting the cycle count.
Bugfix for extract.py
Another bugfix for extract.py
Minor bugfix for extract.py to prevent crashes if .yml file is not found.
Merge branch 'sync' of github.com:jimstevens2001/HybridSim into dev
Set TLB_SIZE to 0 as default to disable that for now. Removed dead code related to pending_sets in prep for update to lock scheme.
Added branches file to explain the repo management.
Moved content in BRANCHES into README file.
Modified locking mechanism to enable higher streaming performance to DRAM.

Previously, a cache hit to DRAM would lock an entire page, which would serialize
subsequent accesses to the same page. The goal of this patch is to allow accesses
to different physical addresses within the same page to go to DRAMSim in parallel,
allowing for higher throughput. It adds the pending_flash_addr map to track
the accesses at a finer granularity and only locks the entire page on a cache miss.
Merge branch 'sandia' into dev
Updated contention_is_locked() to use pending_flash_addr
Merge branch 'dev' into lockfix